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8XC251SA, 8XC251SB,
8XC251SP, 8XC251SQ
Embedded Microcontroller
Users Manual
8XC251SA, 8XC251SB, 8XC251SP, 8XC251SQ
Embedded Microcontroller Users Manual
27279502.qxd 6/18/96 9:25 AM Page 1
Seitenansicht 0
1 2 3 4 5 6 ... 457 458

Inhaltsverzeichnis

Seite 1 - Users Manual

8XC251SA, 8XC251SB,8XC251SP, 8XC251SQEmbedded MicrocontrollerUsers Manual8XC251SA, 8XC251SB, 8XC251SP, 8XC251SQEmbedded Microcontroller Users Manual

Seite 2

8XC251SA, SB, SP, SQ USER’S MANUALviii12.2.2 Power Off Flag ...

Seite 3 - User’s Manual

8XC251SA, SB, SP, SQ USER’S MANUAL5-18.Figure 5-2. Program Status Word RegisterPSWAddress: S:D0HReset State: 0000 0000B7 0CY AC F0 RS1 RS0 OV UD PBit

Seite 4

5-19PROGRAMMING.Figure 5-3. Program Status Word 1 RegisterPSW1Address: S:D1HReset State: 0000 0000B7 0CY AC N RS1 RS0 OV Z —Bit NumberBit MnemonicFun

Seite 6

6Interrupt System

Seite 8

6-1CHAPTER 6INTERRUPT SYSTEM6.1 OVERVIEWThe 8XC251Sx, like other control-oriented computer architectures, employs a program interruptmethod. This oper

Seite 9

8XC251SA, SB, SP, SQ USER’S MANUAL6-2Figure 6-1. Interrupt Control System IE001INT0#Timer 0IE101INT1#Timer 10101ECFECCFxIT0IT15A4149-01IPInterrupt En

Seite 10

6-3INTERRUPT SYSTEM6.2 8XC251SA, SB, SP, SQ INTERRUPT SOURCESFigure 6-1 illustrates the interrupt control system. The 8XC251Sx has eight interrupt sou

Seite 11

8XC251SA, SB, SP, SQ USER’S MANUAL6-46.2.2 Timer InterruptsTwo timer-interrupt request bits TF0 and TF1 (see TCON register, Figure 8-6 on page 8-8) ar

Seite 12

6-5INTERRUPT SYSTEM6.3 PROGRAMMABLE COUNTER ARRAY (PCA) INTERRUPTThe programmable counter array (PCA) interrupt is generated by the logical OR of five

Seite 13

CONTENTSixCHAPTER 14PROGRAMMING AND VERIFYINGNONVOLATILE MEMORY14.1 GENERAL...

Seite 14

8XC251SA, SB, SP, SQ USER’S MANUAL6-6 Figure 6-2. Interrupt Enable RegisterIE0Address: S:A8HReset State: 0000 0000B7 0EA EC ET2 ES ET1 EX1 ET0 E

Seite 15

6-7INTERRUPT SYSTEM6.6 INTERRUPT PRIORITIESEach of the seven 8XC251Sx interrupt sources may be individually programmed to one of fourpriority levels.

Seite 16

8XC251SA, SB, SP, SQ USER’S MANUAL6-8Figure 6-3. Interrupt Priority High RegisterFigure 6-4. Interrupt Priority Low RegisterIPH0Address: S:B7HReset

Seite 17

6-9INTERRUPT SYSTEM6.7 INTERRUPT PROCESSINGInterrupt processing is a dynamic operation that begins when a source requests an interrupt andlasts until

Seite 18

8XC251SA, SB, SP, SQ USER’S MANUAL6-106.7.1 Minimum Fixed Interrupt TimeAll interrupts are sampled or polled every four state times (see Figure 6-5).

Seite 19 - Guide to This Manual

6-11INTERRUPT SYSTEMtime is five states for internal interrupts and six states for external interrupts. External interrupts must remain active for at

Seite 20

8XC251SA, SB, SP, SQ USER’S MANUAL6-12Figure 6-7. Response Time Example #26.7.2.2 Computation of Worst-case Latency With VariablesWorst-case latency

Seite 21 - GUIDE TO THIS MANUAL

6-13INTERRUPT SYSTEM6.7.2.3 Latency CalculationsAssume the use of a zero-wait-state external memory where current instructions, the ISR, and thestack

Seite 22

8XC251SA, SB, SP, SQ USER’S MANUAL6-146.7.2.4 Blocking ConditionsIf all enable and priority requirements have been met, a single prioritized interrupt

Seite 23

6-15INTERRUPT SYSTEM6.7.3 ISRs in ProcessISR execution proceeds until the RETI instruction is encountered. The RETI instruction informsthe processor t

Seite 24

8XC251SA, SB, SP, SQ USER’S MANUALxFIGURESFigure Page2-1 Functional Block Diagram of the 8XC251SA, SB, SP, SQ...

Seite 26

7Input/Output Ports

Seite 28

7-1CHAPTER 7INPUT/OUTPUT PORTS7.1 INPUT/OUTPUT PORT OVERVIEWThe 8XC251Sx uses input/output (I/O) ports to exchange data with external devices. In addi

Seite 29

8XC251SA, SB, SP, SQ USER’S MANUAL7-27.2 I/O CONFIGURATIONSEach port SFR operates via type-D latches, as illustrated in Figure 7-1 for ports 1 and 3.

Seite 30

7-3INPUT/OUTPUT PORTSFigure 7-1. Port 1 and Port 3 StructureFigure 7-2. Port 0 StructureReadLatchReadPinWrite toLatchInternalBusAlternateOutput

Seite 31 - Overview

8XC251SA, SB, SP, SQ USER’S MANUAL7-4Figure 7-3. Port 2 StructureWhen port 0 and port 2 are used for an external memory cycle, an internal control si

Seite 32

7-5INPUT/OUTPUT PORTS7.5 READ-MODIFY-WRITE INSTRUCTIONSSome instructions read the latch data rather than the pin data. The latch based instructions re

Seite 33 - ARCHITECTURAL OVERVIEW

8XC251SA, SB, SP, SQ USER’S MANUAL7-67.6 QUASI-BIDIRECTIONAL PORT OPERATIONPort 1, port 2, and port 3 have fixed internal pullups and are referred to

Seite 34 - 251 Microcontroller Core

7-7INPUT/OUTPUT PORTSFigure 7-4. Internal Pullup Configurations 7.7 PORT LOADINGOutput buffers of port 1, port 2, and port 3 can each sink 1.6 mA at

Seite 35

CONTENTSxiFIGURESFigure Page8-12 T2CON: Timer 2 Control Register ...8-179-1

Seite 36

8XC251SA, SB, SP, SQ USER’S MANUAL7-8The 8XC251Sx CPU writes FFH to the P0 register for all external memory bus cycles. This over-writes previous info

Seite 37 - Figure 2-2. The CPU

7-9INPUT/OUTPUT PORTSNOTEAvoid MOV P0 instructions for external memory accesses. These instructions can corrupt input code bytes at port 0. External s

Seite 39

8Timer/Counters and Watchdog Timer

Seite 41 - Address Spaces

8-1CHAPTER 8TIMER/COUNTERS AND WATCHDOG TIMERThis chapter describes the timer/counters and the watchdog timer (WDT) included as peripheralson the 8XC2

Seite 42

8XC251SA, SB, SP, SQ USER’S MANUAL8-2 Figure 8-1. Basic Logic of the Timer/CountersThe C\Tx# control bit selects timer operation or counter

Seite 43 - ADDRESS SPACES

8-3TIMER/COUNTERS AND WATCHDOG TIMERFor timer operation (C/Tx# = 0), the timer register counts the divided-down system clock. Thetimer register is inc

Seite 44

8XC251SA, SB, SP, SQ USER’S MANUAL8-4For normal timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the se-lected input. Setting

Seite 45 - 51 Architecture

8-5TIMER/COUNTERS AND WATCHDOG TIMER8.3.3 Mode 2 (8-bit Timer With Auto-reload)Mode 2 configures timer 0 as an 8-bit timer (TL0 register) that automat

Seite 46 - A4133-01

8XC251SA, SB, SP, SQ USER’S MANUALxiiFIGURESFigure Page13-23 Bus Diagram for Example 4: 87C251SB/83C251SB in Nonpage Mode ...13-2413-24

Seite 47

8XC251SA, SB, SP, SQ USER’S MANUAL8-6Timer 1 is controlled by the four high-order bits of the TMOD register (Figure 8-5) and bits 7, 6,3, and 2 of the

Seite 48 - A4385-01

8-7TIMER/COUNTERS AND WATCHDOG TIMER Figure 8-5. TMOD: Timer/Counter Mode Control RegisterTMODAddress: S:89HReset State: 0000 0000B7 0GATE1 C/T

Seite 49

8XC251SA, SB, SP, SQ USER’S MANUAL8-8 Figure 8-6. TCON: Timer/Counter Control RegisterWhen timer 0 is in mode 3, it uses timer 1’s overflow fla

Seite 50

8-9TIMER/COUNTERS AND WATCHDOG TIMER8.4.1 Mode 0 (13-bit Timer)Mode 0 configures timer 0 as a 13-bit timer, which is set up as an 8-bit timer (TH1 reg

Seite 51 - • EA# = 1

8XC251SA, SB, SP, SQ USER’S MANUAL8-103. Enter an eight-bit reload value (nR) in register TH0. This can be the same as n0 ordifferent, depending on th

Seite 52

8-11TIMER/COUNTERS AND WATCHDOG TIMERTimer 2 provides the following operating modes: capture mode, auto-reload mode, baud rate gen-erator mode, and pr

Seite 53

8XC251SA, SB, SP, SQ USER’S MANUAL8-128.6.2 Auto-reload Mode The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic

Seite 54 - Memory Address Space

8-13TIMER/COUNTERS AND WATCHDOG TIMER8.6.2.2 Up/Down Counter OperationWhen DCEN = 1, timer 2 operates as an up/down counter (Figure 8-9). External pin

Seite 55 - • R10 is the B-register

8XC251SA, SB, SP, SQ USER’S MANUAL8-148.6.3 Baud Rate Generator ModeThis mode configures timer 2 as a baud rate generator for use with the serial port

Seite 56 - MCS 51 microcontrollers

8-15TIMER/COUNTERS AND WATCHDOG TIMER Figure 8-10. Timer 2: Clock Out Mode . Table 8-3. Timer 2 Modes of OperationModeRCLK OR TCLK(in T2CON)CP

Seite 57

CONTENTSxiiiTABLESTable Page1-1 Intel Application Support Services...1-72

Seite 58

8XC251SA, SB, SP, SQ USER’S MANUAL8-16 Figure 8-11. T2MOD: Timer 2 Mode Control Register8.7 WATCHDOG TIMERThe peripheral section of the 8XC251Sx

Seite 59

8-17TIMER/COUNTERS AND WATCHDOG TIMER Figure 8-12. T2CON: Timer 2 Control RegisterT2CONAddress: S:C8HReset State: 0000 0000B7 0TF2 EXF2 RCLK TCL

Seite 60 - Table 3-7. I/O Port SFRs

8XC251SA, SB, SP, SQ USER’S MANUAL8-188.7.2 Using the WDT To use the WDT to recover from software malfunctions, the user program should control theWDT

Seite 61 - Table 3-8. Serial I/O SFRs

9Programmable Counter Array

Seite 63 - Configuration

9-1CHAPTER 9PROGRAMMABLE COUNTER ARRAYThis chapter describes the programmable counter array (PCA), an on-chip peripheral of the8XC251Sx that performs

Seite 64

8XC251SA, SB, SP, SQ USER’S MANUAL9-29.1.1 Alternate Port UsagePCA modules 3 and 4 share port pins with the real-time wait state and address functions

Seite 65 - DEVICE CONFIGURATION

9-3PROGRAMMABLE COUNTER ARRAYSetting the run control bit (CR in the CCON register) turns the PCA timer/counter on, if the out-put of the NAND gate (Fi

Seite 66 - 16 Kbytes

8XC251SA, SB, SP, SQ USER’S MANUAL9-4 Table 9-1. PCA Special Function Registers (SFRs)Mnemonic Description AddressCLCHPCA Timer/Counter. Thes

Seite 67

9-5PROGRAMMABLE COUNTER ARRAY9.3 PCA COMPARE/CAPTURE MODULESEach compare/capture module is made up of a compare/capture register pair(CCAPxH/CCAPxL),

Seite 68

8XC251SA, SB, SP, SQ USER’S MANUALxivTABLESTable Page10-4 Timer 1 Generated Baud Rates for Serial I/O Modes 1 and 3...1

Seite 69

8XC251SA, SB, SP, SQ USER’S MANUAL9-6To program a compare/capture module for the 16-bit capture mode, program the CAPPx andCAPNx bits in the module’s

Seite 70

9-7PROGRAMMABLE COUNTER ARRAY9.3.2 Compare ModesThe compare function provides the capability for operating the five modules as timers, eventcounters,

Seite 71 - access

8XC251SA, SB, SP, SQ USER’S MANUAL9-8 Figure 9-3. PCA Software Timer and High-speed Output Modes 9.3.4 High-speed Output ModeThe high-speed outpu

Seite 72

9-9PROGRAMMABLE COUNTER ARRAYThe user also has the option of generating an interrupt request when the match occurs by settingthe corresponding interru

Seite 73

8XC251SA, SB, SP, SQ USER’S MANUAL9-10The PCA WDT generates a reset signal each time a match occurs. To hold off a PCA WDT reset,the user has three op

Seite 74 - A4218-02

9-11PROGRAMMABLE COUNTER ARRAY9.3.6 Pulse Width Modulation ModeThe five PCA comparator/capture modules can be independently programmed to function asp

Seite 75

8XC251SA, SB, SP, SQ USER’S MANUAL9-12The value in CCAPxL determines the duty cycle of the current period. The value in CCAPxH de-termines the duty cy

Seite 76

9-13PROGRAMMABLE COUNTER ARRAYFigure 9-7. CMOD: PCA Timer/Counter Mode RegisterCMODAddress: S:D9HReset State: 00XX X000B7 0CIDL WDTE — — — CPS1 CPS0

Seite 77

8XC251SA, SB, SP, SQ USER’S MANUAL9-14 Figure 9-8. CCON: PCA Timer/Counter Control Register CCONAddress: S:D8HReset State: 00X0 0000B7 0CF C

Seite 78

9-15PROGRAMMABLE COUNTER ARRAYFigure 9-9. CCAPMx: PCA Compare/Capture Module Mode RegistersCCAPMx (x = 0–4)Address: CCAPM0 S:DAHCCAPM1 S:DBHCCAPM2 S

Seite 79

CONTENTSxvTABLESTable PageC-4 Serial I/O SFRs ...

Seite 81 - Programming

10Serial I/O Port

Seite 83 - CHAPTER 5

10-1CHAPTER 10SERIAL I/O PORTThe serial input/output port supports communication with modems and other external peripheraldevices. This chapter provid

Seite 84 - Table 5-1. Data Types

8XC251SA, SB, SP, SQ USER’S MANUAL10-2 Figure 10-1. Serial Port Block DiagramTable 10-2. Serial Port Special Function RegistersMnemonic Descr

Seite 85

10-3SERIAL I/O PORTThe serial port control (SCON) register (Figure 10-2) configures and controls the serial port. Figure 10-2. SCON: Serial Por

Seite 86

8XC251SA, SB, SP, SQ USER’S MANUAL10-4 Figure 10-2. SCON: Serial Port Control Register (Continued)10.2 MODES OF OPERATIONThe serial I/O port can

Seite 87 - 5.3.1.3 Direct

10-5SERIAL I/O PORT Figure 10-3. Mode 0 Timing10.2.1.2 Reception (Mode 0)To start a reception in mode 0, write to the SCON register. Clear bits S

Seite 88 - 5.3.1.4 Indirect

8XC251SA, SB, SP, SQ USER’S MANUAL10-610.2.2 Asynchronous Modes (Modes 1, 2, and 3)The serial port has three asynchronous modes of operation. • Mode 1

Seite 89 - 251 Architecture

10-7SERIAL I/O PORT10.3 FRAMING BIT ERROR DETECTION (MODES 1, 2, AND 3)Framing bit error detection is provided for the three asynchronous modes. To en

Seite 91

8XC251SA, SB, SP, SQ USER’S MANUAL10-8Implemented in hardware, automatic address recognition enhances the multiprocessor communi-cation feature by all

Seite 92

10-9SERIAL I/O PORTThe SADEN byte is selected so that each slave may be addressed separately. For Slave A, bit 0(the LSB) is a don't-care bit; fo

Seite 93

8XC251SA, SB, SP, SQ USER’S MANUAL10-1010.5.3 Reset AddressesOn reset, the SADDR and SADEN registers are initialized to 00H, i.e., the given and broad

Seite 94

10-11SERIAL I/O PORT10.6.3.1 Timer 1 Generated Baud Rates (Modes 1 and 3)Timer 1 is the default baud rate generator for the transmitter and the receiv

Seite 95

8XC251SA, SB, SP, SQ USER’S MANUAL10-1210.6.3.3 Timer 2 Generated Baud Rates (Modes 1 and 3)Timer 2 may be selected as the baud rate generator for the

Seite 96

10-13SERIAL I/O PORTYou may configure timer 2 as a timer or a counter. In most applications, it is configured for timeroperation (i.e., the C/T2# bit

Seite 97

8XC251SA, SB, SP, SQ USER’S MANUAL10-14Note that timer 2 increments every state time (2TOSC) when it is in the baud rate generator mode.In the baud ra

Seite 98

11Minimum Hardware Setup

Seite 100

11-1CHAPTER 11MINIMUM HARDWARE SETUPThis chapter discusses the basic operating requirements of the MCS® 251 microcontroller and de-scribes a minimum h

Seite 101 - PROGRAMMING

1Guide to This Manual

Seite 102

8XC251SA, SB, SP, SQ USER’S MANUAL11-211.2 ELECTRICAL ENVIRONMENTThe 8XC251Sx is a high-speed CHMOS device. To achieve satisfactory performance, its o

Seite 103 - Interrupt System

11-3MINIMUM HARDWARE SETUP11.3 CLOCK SOURCESThe 8XC251Sx can obtain the system clock signal from an external clock source (Figure 11-3) orit can gener

Seite 104

8XC251SA, SB, SP, SQ USER’S MANUAL11-4For a more in-depth discussion of crystal specifications, ceramic resonators, and the selection ofC1 and C2 see

Seite 105 - INTERRUPT SYSTEM

11-5MINIMUM HARDWARE SETUPFor external clock drive requirements, see the device data sheet. Figure 11-4 shows the clockdrive waveform. The external cl

Seite 106 - Interrupt Polling Sequence

8XC251SA, SB, SP, SQ USER’S MANUAL11-6The power off flag (POF) in the PCON register indicates whether a reset is a warm start or a coldstart. A cold s

Seite 107

11-7MINIMUM HARDWARE SETUPWhile the RST pin is high ALE, PSEN#, and the port pins are weakly pulled high. The first ALEoccurs 32TOSC after the reset s

Seite 108

8XC251SA, SB, SP, SQ USER’S MANUAL11-8 Figure 11-5. Reset Timing Sequence RSTXTALInternal ResetRoutineALEA4103-01PSEN#≥ 64 TOSC12332First ALE

Seite 109

12Special Operating Modes

Seite 111 - Table 6-4. Level of Priority

12-1CHAPTER 12SPECIAL OPERATING MODESThis chapter describes the power control (PCON) register and three special operating modes: idle,powerdown, and o

Seite 114

8XC251SA, SB, SP, SQ USER’S MANUAL12-2 Figure 12-1. Power Control (PCON) RegisterPCONAddress: S:87HReset State: 00XX 0000B7 0SMOD1 SMOD0 — POF GF

Seite 115

12-3SPECIAL OPERATING MODES Figure 12-2. Idle and Powerdown Clock ControlTable 12-1. Pin Conditions in Various ModesModeProgram MemoryALEPi

Seite 116 - Response Time = 4

8XC251SA, SB, SP, SQ USER’S MANUAL12-412.3 IDLE MODEIdle mode is a power reduction mode that reduces power consumption to about 40% of normal.In this

Seite 117 - 6.7.2.3 Latency Calculations

12-5SPECIAL OPERATING MODES12.3.2 Exiting Idle ModeThere are two ways to exit idle mode: • Generate an enabled interrupt. Hardware clears the PCON reg

Seite 118

8XC251SA, SB, SP, SQ USER’S MANUAL12-612.4.1 Entering Powerdown ModeTo enter powerdown mode, set the PCON register PD bit. The 8XC251Sx enters the pow

Seite 119

12-7SPECIAL OPERATING MODES12.5 ON-CIRCUIT EMULATION (ONCE) MODEThe on-circuit emulation (ONCE) mode permits external testers to test and debug 8XC251

Seite 121 - Input/Output Ports

13External Memory Interface

Seite 123 - INPUT/OUTPUT PORTS

13-1CHAPTER 13EXTERNAL MEMORY INTERFACE13.1 OVERVIEWThe external memory interface comprises the external bus (ports 0 and 2, and when enabled alsoincl

Seite 124

1-1CHAPTER 1GUIDE TO THIS MANUALThis manual describes the 8XC251SA, SB, SP, SQ† embedded microcontroller, which is the firstmember of the Intel MCS® 2

Seite 125 - Figure 7-2. Port 0 Structure

8XC251SA, SB, SP, SQ USER’S MANUAL13-2 Table 13-1. External Memory Interface SignalsSignalNameType DescriptionAlternateFunctionA17 O Address Lin

Seite 126 - Figure 7-3. Port 2 Structure

13-3EXTERNAL MEMORY INTERFACE13.2 EXTERNAL BUS CYCLESThe section describes the bus cycles the 8XC251Sx executes to fetch code, read data, and writedat

Seite 127

8XC251SA, SB, SP, SQ USER’S MANUAL13-413.2.2 Nonpage Mode Bus CyclesIn nonpage mode, the external bus structure is the same as for MCS 51 microcontrol

Seite 128

13-5EXTERNAL MEMORY INTERFACE Figure 13-4. External Data Write (Nonpage Mode) 13.2.3 Page Mode Bus CyclesPage mode increases performance by reducing

Seite 129

8XC251SA, SB, SP, SQ USER’S MANUAL13-6Figure 13-5 shows the two types of external bus cycles for code fetches in page mode. The page-miss cycle is the

Seite 130

13-7EXTERNAL MEMORY INTERFACE Figure 13-6. External Data Read (Page Mode) Figure 13-7. External Data Write (Page Mode) A17/A16/P0P2ALERD#/PSEN

Seite 131

8XC251SA, SB, SP, SQ USER’S MANUAL13-813.3 WAIT STATESThe 8XC251SA, SB, SP, SQ provides three types of wait state solutions to external memory prob-le

Seite 132

13-9EXTERNAL MEMORY INTERFACE Figure 13-8. External Code Fetch (Nonpage Mode, One RD#/PSEN# Wait State) Figure 13-9. External Data Write (Nonp

Seite 133 - Watchdog Timer

8XC251SA, SB, SP, SQ USER’S MANUAL13-1013.4.2 Extending ALEFigure 13-10 shows the nonpage mode code fetch external bus cycle with ALE extended. Thewai

Seite 134

13-11EXTERNAL MEMORY INTERFACEFigure 13-11. Real-time Wait State Control Register (WCON) NOTEThe WAIT# and WCLK signals are alternate functions for t

Seite 135 - CHAPTER 8

8XC251SA, SB, SP, SQ USER’S MANUAL1-2Chapter 7, “Input/Output Ports” — describes the four 8-bit I/O ports (ports 0–3) and discussestheir configuration

Seite 136 - Overflow

8XC251SA, SB, SP, SQ USER’S MANUAL13-1213.5.1 Real-time WAIT# Enable (RTWE)The real-time WAIT# input is enabled by writing a logical ‘1’ to the WCON.0

Seite 137 - Table 8-2. External Signals

13-13EXTERNAL MEMORY INTERFACEFigure 13-12. External Code Fetch/Data Read (Nonpage Mode, RT Wait State)Figure 13-13. External Data Write (Nonpage Mo

Seite 138

8XC251SA, SB, SP, SQ USER’S MANUAL13-14Figure 13-14. External Data Read (Page Mode, RT Wait State)Figure 13-15. External Data Write (Page Mode, RT W

Seite 139

13-15EXTERNAL MEMORY INTERFACE13.6 CONFIGURATION BYTE BUS CYCLESIf EA# = 0, devices obtain configuration information from a configuration array in ext

Seite 140 - A4112-02

8XC251SA, SB, SP, SQ USER’S MANUAL13-1613.7 PORT 0 AND PORT 2 STATUSThis section summarizes the status of the port 0 and port 2 pins when these ports

Seite 141

13-17EXTERNAL MEMORY INTERFACE13.7.2 Port 0 and Port 2 Pin Status in Page ModeIn a page-mode bus cycle, the data is multiplexed with the upper address

Seite 142

8XC251SA, SB, SP, SQ USER’S MANUAL13-1813.8 EXTERNAL MEMORY DESIGN EXAMPLES This section presents several external memory designs for 8XC251Sx systems

Seite 143

13-19EXTERNAL MEMORY INTERFACE Figure 13-18. Address Space for Example 1 A4220-021056 Bytes On-chip RAM01:00:FE:FF:128 Kbytes External FlashAddres

Seite 144

8XC251SA, SB, SP, SQ USER’S MANUAL13-2013.8.2 Example 2: RD1:0 = 01, 17-bit Bus, External Flash and RAMIn this example, an 80C251SB operates in page m

Seite 145

13-21EXTERNAL MEMORY INTERFACE Figure 13-20. Address Space for Example 2 A4168-031056 Bytes On-chip RAM01:00:FE:FF:64 Kbytes External FlashAddres

Seite 146 - 8.6.2.1 Up Counter Operation

1-3GUIDE TO THIS MANUALAppendix B, “Signal Descriptions” — describes the function(s) of each device pin. Descrip-tions are listed alphabetically by si

Seite 147 - A4114-01

8XC251SA, SB, SP, SQ USER’S MANUAL13-2213.8.3 Example 3: RD1:0 = 01, 17-bit Bus, External RAMIn this example, an 87C251SB/83C251SB operates in nonpage

Seite 148 - 4 (65536 - RCAP2H, RCAP2L)×

13-23EXTERNAL MEMORY INTERFACE Figure 13-22. Address Space for Example 3 A4169-031056 Bytes On-chip RAM01:00:FE:FF:16 Kbytes On-chip Code MemoryAd

Seite 149 - A4116-02

8XC251SA, SB, SP, SQ USER’S MANUAL13-2413.8.4 Example 4: RD1:0 = 10, 16-bit Bus, External RAMIn this example, an 87C251SB/83C251SB operates in nonpage

Seite 150

13-25EXTERNAL MEMORY INTERFACE Figure 13-24. Address Space for Example 4 A4224-021056 Bytes On-chip RAM01:00:FE:FF:16 Kbytes On-chip Code MemoryAd

Seite 151

8XC251SA, SB, SP, SQ USER’S MANUAL13-2613.8.5 Example 5: RD1:0 = 11, 16-bit Bus, External EPROM and RAM In this example, an 80C251SB operates in nonpa

Seite 152

13-27EXTERNAL MEMORY INTERFACE Figure 13-25. Bus Diagram for Example 5: 80C251SB in Nonpage Mode A4145-01A7:0LatchA15:8A/D7:0EPROM(64 Kbytes)OE#C

Seite 153 - Counter Array

8XC251SA, SB, SP, SQ USER’S MANUAL13-28 Figure 13-26. Address Space for Examples 5 and 6 1056 BytesOn-chip RAM01:00:FE:FF:64 Kbytes External EPR

Seite 154

13-29EXTERNAL MEMORY INTERFACE13.8.6 Example 6: RD1:0 = 11, 16-bit Bus, External EPROM and RAMIn this example, an 80C251SB operates in page mode with

Seite 155 - PROGRAMMABLE COUNTER ARRAY

8XC251SA, SB, SP, SQ USER’S MANUAL13-3013.8.7 Example 7: RD1:0 = 01, 17-bit Bus, External FlashIn this example, an 80C251SB operates in page mode with

Seite 156

14Programming and Verifying Nonvolatile Memory

Seite 157 - (16 Bits)

8XC251SA, SB, SP, SQ USER’S MANUAL1-4Instructions Instruction mnemonics are shown in upper case to avoid confusion.When writing code, either upper cas

Seite 159 - • No operation

14-1CHAPTER 14PROGRAMMING AND VERIFYINGNONVOLATILE MEMORYThis chapter provides instructions for programming and verifying on-chip nonvolatile memoryon

Seite 160 - A4163-02

8XC251SA, SB, SP, SQ USER’S MANUAL14-2In some microcontroller applications, it is desirable that user program code be secure from unau-thorized access

Seite 161

14-3PROGRAMMING AND VERIFYING NONVOLATILE MEMORY14.1.2 EPROM DevicesOn EPROM devices, the quartz window must be covered with an opaque label when the

Seite 162 - A4164-01

8XC251SA, SB, SP, SQ USER’S MANUAL14-4 Table 14-1. Programming and Verifying Modes Mode RST PSEN# VPP PROG# Port0Port2AddressPort 1 (high)Port 3

Seite 163

14-5PROGRAMMING AND VERIFYING NONVOLATILE MEMORY Figure 14-1. Setup for Programming and Verifying Nonvolatile Memory 14.4 PROGRAMMING ALGORITHMT

Seite 164 - A4165-01

8XC251SA, SB, SP, SQ USER’S MANUAL14-6 Figure 14-2. Program/Verify Bus Cycles 14.5 VERIFY ALGORITHMUse this procedure to verify user program code

Seite 165 - A4166-01

14-7PROGRAMMING AND VERIFYING NONVOLATILE MEMORY14.6.1 On-chip Code MemoryOn-chip code memory is located in the top region of the memory space startin

Seite 166 - A4161-01

8XC251SA, SB, SP, SQ USER’S MANUAL14-8 14.6.4 Encryption ArrayThe 87C251Sx and 83C251Sx controllers include a 128-byte encryption array located in

Seite 167

14-9PROGRAMMING AND VERIFYING NONVOLATILE MEMORY 14.7 VERIFYING THE 83C251SA, SB, SP, SQ (ROM)Nonvolatile memory on the 83C251Sx controller is facto

Seite 168 - Table 9-3. PCA Module Modes

1-5GUIDE TO THIS MANUALUnits of Measure The following abbreviations are used to represent units of measure:A amps, amperesDCV direct current voltsKbyt

Seite 170

AInstruction Set Reference

Seite 172

A-1APPENDIX AINSTRUCTION SET REFERENCEThis appendix contains reference material for the instructions in the MCS® 251 architecture. Itincludes an opcod

Seite 173 - SERIAL I/O PORT

8XC251SA, SB, SP, SQ USER’S MANUALA-2A.1 NOTATION FOR INSTRUCTION OPERANDS Table A-1. Notation for Register OperandsRegister NotationMCS® 251Arch.MCS

Seite 174 - A4123-02

A-3INSTRUCTION SET REFERENCETable A-2. Notation for Direct AddressesDirectAddress.DescriptionMCS® 251Arch.MCS 51Arch.dir8 An 8-bit direct address. Th

Seite 175

8XC251SA, SB, SP, SQ USER’S MANUALA-4A.2 OPCODE MAP AND SUPPORTING TABLESTable A-6. Instructions for MCS® 51 MicrocontrollersBin. 0 1 2 3 4 5 6-7 8-F

Seite 176

A-5INSTRUCTION SET REFERENCE Table A-7. New Instructions for the MCS® 251 ArchitectureBin. A5x8A5x9A5xAA5xBA5xCA5xDA5xEA5xFSrc.x8x9xAxBxCx

Seite 177 - Transmit

8XC251SA, SB, SP, SQ USER’S MANUALA-6 Table A-8. Data InstructionsInstruction Byte 0 Byte 1 Byte 2 Byte 3Oper Rmd,Rms x C md msOper WRjd,WRjs x D

Seite 178 - A2261-01

A-7INSTRUCTION SET REFERENCEAll of the bit instructions in the MCS 251 architecture (Table A-7) have opcode A9, which servesas an escape byte (similar

Seite 179

8XC251SA, SB, SP, SQ USER’S MANUAL1-61.3.1 Data Sheet The data sheet is included in Embedded Microcontrollers and is also available individually.8XC25

Seite 180

8XC251SA, SB, SP, SQ USER’S MANUALA-8Table A-12. PUSH/POP Instructions Instruction Byte 0(x) Byte 1 Byte 2 Byte 3PUSH #data C A 0000 0010 #dataPUSH

Seite 181

A-9INSTRUCTION SET REFERENCETable A-14. Displacement/Extended MOVsInstruction Byte 0 Byte 1 Byte 2 Byte 3MOV Rm,@WRj+dis 0 9 m j/2 dis[15:8] dis[7:0

Seite 182

8XC251SA, SB, SP, SQ USER’S MANUALA-10Table A-15. INC/DECInstruction Byte 0 Byte 11 INC Rm,#short 0 B m 00 ss2 INC WRj,#short 0 B j/2 01 ss3 INC

Seite 183

A-11INSTRUCTION SET REFERENCEA.3 INSTRUCTION SET SUMMARYThis section summarizes the MCS 251 architecture instruction set. Tables A-19 through A-27 lis

Seite 184

8XC251SA, SB, SP, SQ USER’S MANUALA-12Table A-18. State Times to Access the Port SFRsInstructionCase 0Execution TimesAdditional State TimesBinary Sou

Seite 185 - A4120-01

A-13INSTRUCTION SET REFERENCEORL CY,/bit51 1 1 1 2 3 4ORL dir8,#data 3 3 1 2 3 4ORL dir8,A 2 2 2 4 6 8ORL Rm,dir8 3 2 1 2 3 4SETB bit 432468SETB bit51

Seite 186

8XC251SA, SB, SP, SQ USER’S MANUALA-14A.3.2 Instruction Summaries Table A-19. Summary of Add and Subtract InstructionsAdd ADD <dest>,<

Seite 187 - Minimum Hardware

A-15INSTRUCTION SET REFERENCE Table A-20. Summary of Compare InstructionsCompare CMP <dest>,<src> dest opnd – src opndMnemonic <dest

Seite 188

8XC251SA, SB, SP, SQ USER’S MANUALA-16 Table A-21. Summary of Increment and Decrement InstructionsIncrement INC DPTR (DPTR)

Seite 189 - Figure 11-1. Minimum Setup

A-17INSTRUCTION SET REFERENCETable A-23. Summary of Logical Instructions Logical AND ANL <dest>,<src> dest opnd ←dest opnd Λ src opndLogi

Seite 190

1-7GUIDE TO THIS MANUAL1.4 APPLICATION SUPPORT SERVICESYou can get up-to-date technical information from a variety of electronic support systems: theW

Seite 191 - MINIMUM HARDWARE SETUP

8XC251SA, SB, SP, SQ USER’S MANUALA-18SRARm Shift byte reg right through the MSB 3 2 2 1WRj Shift word reg right through the MSB 3 2 2 1SRLRm Shift by

Seite 192 - Clock Driver

A-19INSTRUCTION SET REFERENCETable A-24. Summary of Move Instructions Move (2) MOV <dest>,<src> destination ← src opndMove with Sign Exte

Seite 193

8XC251SA, SB, SP, SQ USER’S MANUALA-20MOVDRk,dir8 Dir addr to dword reg 4 6 3 5DRk,dir16 Dir addr (64K) to dword reg 5 6 4 5Rm,dir8 Dir addr to byte r

Seite 194

A-21INSTRUCTION SET REFERENCEMOV@WRj+dis16,WRj Word reg to Indir addr with disp (64K) 5 7 4 6@DRk+dis24,Rm Byte reg to Indir addr with disp (16M) 5 7

Seite 195

8XC251SA, SB, SP, SQ USER’S MANUALA-22Table A-25. Summary of Exchange, Push, and Pop Instructions Exchange Contents XCH <dest>,<src> A ↔

Seite 196 - First ALE

A-23INSTRUCTION SET REFERENCETable A-26. Summary of Bit Instructions Clear Bit CLR bit bit ← 0Set Bit SETB bit bit ← 1Complement Bit CPL bit bit← Øbi

Seite 197 - Special Operating

8XC251SA, SB, SP, SQ USER’S MANUALA-24Table A-27. Summary of Control Instructions Mnemonic <dest>,<src> NotesBinary Mode Source ModeBytes

Seite 198

A-25INSTRUCTION SET REFERENCEJSLE rel Jump if less than or equal (signed) 3 2/5 2 1/4JSG rel Jump if greater than (signed) 3 2/5 2 1/4JSGE rel Jump i

Seite 199 - SPECIAL OPERATING MODES

8XC251SA, SB, SP, SQ USER’S MANUALA-26A.4 INSTRUCTION DESCRIPTIONSThis section describes each instruction in the MCS 251 architecture. See the note on

Seite 200

A-27INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: ACALL (PC) ← (PC) + 2 (SP) ← (SP) + 1 ((SP)) ←

Seite 201 - A4160-01

8XC251SA, SB, SP, SQ USER’S MANUAL1-81.4.3 FaxBack ServiceThe FaxBack service is an on-demand publishing system that sends documents to your fax ma-ch

Seite 202

8XC251SA, SB, SP, SQ USER’S MANUALA-28Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: ADD (A) ← (A) + #dataADD A,dir8Binary Mo

Seite 203

A-29INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: ADD (Rmd) ← (Rmd) + (Rms) ADD WRjd,WRjs

Seite 204

8XC251SA, SB, SP, SQ USER’S MANUALA-30ADD WRj,#data16Binary Mode Source ModeBytes: 54States: 43[Encoding] Hex Code in: Binary Mode = [A5][Encoding]Sou

Seite 205

A-31INSTRUCTION SET REFERENCEHex Code in: Binary Mode = [A5][Encoding]Source Mode = [EncodingOperation: ADD (WRj) ← (WRj) + (dir8)ADD Rm,dir16Binary M

Seite 206

8XC251SA, SB, SP, SQ USER’S MANUALA-32ADD Rm,@DRkBinary Mode Source ModeBytes: 43States: 43[Encoding]Hex Code in: Binary Mode = [A5][Encoding]Source M

Seite 207 - Interface

A-33INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: ADDC (A) ← (A) + (CY) + #data ADDC A,dir8Binary

Seite 208

8XC251SA, SB, SP, SQ USER’S MANUALA-34AJMP addr11 Function: Absolute jump Description: Transfers program execution to the specified address, which is

Seite 209 - EXTERNAL MEMORY INTERFACE

A-35INSTRUCTION SET REFERENCEExample: Register 1 contains 0C3H (11000011B) and register 0 contains 55H (01010101B). After executing the instruction AN

Seite 210

8XC251SA, SB, SP, SQ USER’S MANUALA-36Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: ANL (A) ← (A) Λ #data ANL A,dir8Binary M

Seite 211 - • The chip is in idle mode

A-37INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: ANL (Rmd) ← (Rmd) Λ (Rms) ANL WRjd,WRjsBi

Seite 212 - A4230-01

1-9GUIDE TO THIS MANUALAny customer with a PC and modem can access the BBS. The system provides automatic config-uration support for 1200- through 192

Seite 213

8XC251SA, SB, SP, SQ USER’S MANUALA-38ANL Rm,dir8Binary Mode Source ModeBytes: 43States: 3† 2††If this instruction addresses a port (Px, x = 0–3), add

Seite 214 - A2809-04

A-39INSTRUCTION SET REFERENCE[Encoding] Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: ANL (WRj) ← (WRj) Λ (dir16)ANL Rm,

Seite 215

8XC251SA, SB, SP, SQ USER’S MANUALA-40Flags:Example: Set the CY flag if, and only if, P1.0 = 1, ACC. 7 = 1, and OV = 0: MOV CY,P1.0 ;Load carry with

Seite 216

A-41INSTRUCTION SET REFERENCEOperation: ANL (CY) ← (CY) Λ (bit) ANL CY,/bitBinary Mode Source ModeBytes: 43States: 3† 2††If this instruction addresses

Seite 217

8XC251SA, SB, SP, SQ USER’S MANUALA-42VariationsCJNE A,#data,rel Binary Mode Source ModeNot Taken Taken Not Taken TakenBytes: 33 33States: 25 25Hex Co

Seite 218 - A2813-04

A-43INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding]Source Mode = [A5][Encoding]Operation: (PC) ← (PC) + 3IF ((Ri)) ≠ #dataTHEN (PC

Seite 219

8XC251SA, SB, SP, SQ USER’S MANUALA-44Binary Mode Source ModeBytes: 11States: 11Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation

Seite 220

A-45INSTRUCTION SET REFERENCEHex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: CLR (CY) ← 0 CLR bitBinary Mode Source ModeBytes:

Seite 221 - A5009-01

8XC251SA, SB, SP, SQ USER’S MANUALA-46 Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: CMP(Rmd) – (Rms) CMP WRjd,WRjs

Seite 222 - A5008-01

A-47INSTRUCTION SET REFERENCECMP WRj,#data16Binary Mode Source ModeBytes: 54States: 43[Encoding] Hex Code in: Binary Mode = [A5][Encoding]Source Mode

Seite 223 - A4228-01

May 1996 Order Number 272795-0028XC251SA, 8XC251SB, 8XC251SP, 8XC251SQEmbedded MicrocontrollerUser’s Manual

Seite 225

8XC251SA, SB, SP, SQ USER’S MANUALA-48 Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: CMP (Rm) – (dir8) CMP WRj,dir8B

Seite 226 - A4219-01

A-49INSTRUCTION SET REFERENCECMP Rm,@WRjBinary Mode Source ModeBytes: 43States: 32[Encoding]Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [En

Seite 227 - A4220-02

8XC251SA, SB, SP, SQ USER’S MANUALA-50Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: CPL (A) ← Ø(A)CPL bit Function: Compleme

Seite 228 - A4148-01

A-51INSTRUCTION SET REFERENCEOperation: CPL (CY) ← Ø(CY)CPL bitBinary Mode Source ModeBytes: 43States: 4† 3††If this instruction addresses a port (Px,

Seite 229

8XC251SA, SB, SP, SQ USER’S MANUALA-52Example: The accumulator contains 56H (01010110B), which represents the packed BCD digits of the decimal number

Seite 230 - A4147-02

A-53INSTRUCTION SET REFERENCEExample: Register 0 contains 7FH (01111111B). On-chip RAM locations 7EH and 7FH contain 00H and 40H, respectively. After

Seite 231 - A4169-03

8XC251SA, SB, SP, SQ USER’S MANUALA-54DEC RnBinary Mode Source ModeBytes: 12States: 12Hex Code in: Binary Mode = [Encoding]Source Mode = [A5][Encoding

Seite 232 - A4221-01

A-55INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: DEC (WRj) ← (WRj) – #shortDEC DRk,#shortB

Seite 233

8XC251SA, SB, SP, SQ USER’S MANUALA-56VariationsDIV Rmd RmsBinary Mode Source ModeBytes: 32States: 11 10Hex Code in: Binary Mode = [A5][Encoding]Sourc

Seite 234

A-57INSTRUCTION SET REFERENCEException: if register B contains 00H, the values returned in the accumulator and register B are undefined; the CY flag i

Seite 235

2Architectural Overview

Seite 236

8XC251SA, SB, SP, SQ USER’S MANUALA-58Example: The on-chip RAM locations 40H, 50H, and 60H contain 01H, 70H, and 15H, respectively. After executing th

Seite 237

A-59INSTRUCTION SET REFERENCEOperation: DJNZ (PC) ← (PC) + 2 (Rn) ← (Rn) – 1 IF (Rn) > 0 or (Rn) < 0 THEN (PC) ← (PC)

Seite 238 - A4151-01

8XC251SA, SB, SP, SQ USER’S MANUALA-60ECALL @DRkBinary Mode Source ModeBytes: 32States: 12 11Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [E

Seite 239 - Verifying Nonvolatile

A-61INSTRUCTION SET REFERENCEEJMP @DRkBinary Mode Source ModeBytes: 32States: 76Hex Code in: Binary Mode = [A5] [Encoding]Source Mode = [Encoding]Oper

Seite 240

8XC251SA, SB, SP, SQ USER’S MANUALA-62Flags:Example: Register 0 contains 7EH (011111110B) and on-chip RAM locations 7EH and 7FH contain 0FFH and 40H,

Seite 241 - NONVOLATILE MEMORY

A-63INSTRUCTION SET REFERENCEOperation: INC ((Ri) ← ((Ri)) + 1 INC RnBinary Mode Source ModeBytes: 12States: 12Hex Code in: Binary Mode = [Encoding]So

Seite 242

8XC251SA, SB, SP, SQ USER’S MANUALA-64Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: INC (WRj) ← (WRj) + #shortINC DRk,#s

Seite 243

A-65INSTRUCTION SET REFERENCEJB bit51,rel JB bit,relFunction: Jump if bit set Description: If the specified bit is a one, jump to the address specifie

Seite 244

8XC251SA, SB, SP, SQ USER’S MANUALA-66Operation: JB (PC) ← (PC) + 3 IF (bit) = 1 THEN (PC) ← (PC) + relJBC bit51,rel JBC bit

Seite 245 - A4122-02

A-67INSTRUCTION SET REFERENCEJBC bit,relBinary Mode Source ModeNot Taken Taken Not Taken TakenBytes: 5 5 4 4States: 47 36[Encoding]Hex Code in: Binary

Seite 247

8XC251SA, SB, SP, SQ USER’S MANUALA-68Operation: JC (PC) ← (PC) + 2 IF (CY) = 1 THEN (PC) ← (PC) + rel JE rel Function: Jump if

Seite 248

A-69INSTRUCTION SET REFERENCEExample: The instructionJG LABEL1 causes program execution to continue at label LABEL1 if the Z flag and the CY flag are

Seite 249

8XC251SA, SB, SP, SQ USER’S MANUALA-70Operation: JLE(PC) ← (PC) + 2 IF (Z) = 1 OR (CY) = 1 THEN (PC) ← (PC) + rel JMP @A+DPTR Function: Jump

Seite 250

A-71INSTRUCTION SET REFERENCEFlags:Example: Input port 1 contains 11001010B and the accumulator contains 56H (01010110B). After executing the instruct

Seite 251 - Reference

8XC251SA, SB, SP, SQ USER’S MANUALA-72JNC rel Function: Jump if carry not set Description: If the CY flag is clear, branch to the address specified; o

Seite 252

A-73INSTRUCTION SET REFERENCEBinary Mode Source ModeNot Taken Taken Not Taken TakenBytes: 33 22States: 25 14Hex Code in: Binary Mode = [A5][Encoding]S

Seite 253 - INSTRUCTION SET REFERENCE

8XC251SA, SB, SP, SQ USER’S MANUALA-74JSG rel Function: Jump if greater than (signed)Description: If the Z flag is clear AND the N flag and the OV fla

Seite 254

A-75INSTRUCTION SET REFERENCEBinary Mode Source ModeNot Taken Taken Not Taken TakenBytes: 33 22States: 25 14Hex Code in: Binary Mode = [A5][Encoding]S

Seite 255

8XC251SA, SB, SP, SQ USER’S MANUALA-76JSLE rel Function: Jump if less than or equal (signed)Description: If the Z flag is set OR if the the N flag and

Seite 256 - 51 Microcontrollers

A-77INSTRUCTION SET REFERENCEExample: The accumulator contains 01H. After executing the instruction sequence JZ LABEL1DEC A JZ LABEL2 the accumulator

Seite 257 -

2-1CHAPTER 2ARCHITECTURAL OVERVIEWThe 8XC251Sx is the first member of the MCS®251 microcontroller family. This family of 8-bitmicrocontrollers is a hi

Seite 258 - Table A-8. Data Instructions

8XC251SA, SB, SP, SQ USER’S MANUALA-78Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding]Operation: LCALL (PC) ← (PC) + 3 (SP) ← (SP) + 1

Seite 259 - Table A-10. Bit Instructions

A-79INSTRUCTION SET REFERENCEHex Code in: Binary Mode = [Encoding] Source Mode = [Encoding]Operation: LJMP (PC) ← (addr.15:0)LJMP @WRj Binary Mode So

Seite 260

8XC251SA, SB, SP, SQ USER’S MANUALA-80Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding]Operation: MOV (A) ← #data MOV dir8,#data Binary

Seite 261

A-81INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding] Source Mode = [Encoding]Operation: MOV (dir8) ← (dir8) MOV dir8,@Ri Binary Mod

Seite 262 - Table A-17. Shifts

8XC251SA, SB, SP, SQ USER’S MANUALA-82MOV Rn,dir8 Binary Mode Source ModeBytes: 23States: 1† 2††If this instruction addresses a port (Px, x = 0–3), ad

Seite 263

A-83INSTRUCTION SET REFERENCEOperation: MOV (A) ← (Rn) MOV dir8,A Binary Mode Source ModeBytes: 22States: 2† 2††If this instruction addresses a port (

Seite 264

8XC251SA, SB, SP, SQ USER’S MANUALA-84Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding]Operation: MOV (Rmd) ← (Rms) MOV WRjd,WRjs Bi

Seite 265

A-85INSTRUCTION SET REFERENCE[Encoding]Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding]Operation: MOV (WRj) ← #data16 MOV DRk,#0dat

Seite 266

8XC251SA, SB, SP, SQ USER’S MANUALA-86Operation: MOV (Rm) ← (dir8)MOV WRj,dir8 Binary Mode Source ModeBytes: 43States: 43Hex Code in: Binary Mode = [

Seite 267

A-87INSTRUCTION SET REFERENCE[Encoding]Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding]Operation: MOV (WRj) ← (dir16)MOV DRk,dir16 B

Seite 268

8XC251SA, SB, SP, SQ USER’S MANUAL2-2 Figure 2-1. Functional Block Diagram of the 8XC251SA, SB, SP, SQ SRC2 (8)Code Address (24)Clock & Reset

Seite 269

8XC251SA, SB, SP, SQ USER’S MANUALA-88MOV WRjd,@WRjs Binary Mode Source ModeBytes: 43States: 43[Encoding]Hex Code in: Binary Mode = [A5][Encoding] So

Seite 270

A-89INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding]Operation: MOV (dir8) ← (WRj) MOV dir8,DRk Binary Mo

Seite 271

8XC251SA, SB, SP, SQ USER’S MANUALA-90MOV dir16,DRk Binary Mode Source ModeBytes: 54States: 76[Encoding]Hex Code in: Binary Mode = [A5][Encoding] Sou

Seite 272

A-91INSTRUCTION SET REFERENCEHex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding]Operation: MOV ((WRjd)) ← (WRjs)MOV @DRk,WRj Binary Mo

Seite 273

8XC251SA, SB, SP, SQ USER’S MANUALA-92MOV Rm,@DRk + dis24 Binary Mode Source ModeBytes: 54States: 76[Encoding]Hex Code in: Binary Mode = [A5][Encodin

Seite 274

A-93INSTRUCTION SET REFERENCE[Encoding]Hex Code in: Binary Mode = [A5][Encoding] Source Mode = [Encoding]Operation: MOV ((WRj)) + (dis) ← (WRj)MOV @D

Seite 275

8XC251SA, SB, SP, SQ USER’S MANUALA-94Example: The CY flag is set, input Port 3 contains 11000101B, and output Port 1 contains 35H (00110101B). After

Seite 276

A-95INSTRUCTION SET REFERENCEOperation: MOV (bit) ← (CY)MOV CY,bitBinary Mode Source ModeBytes: 43States: 3† 2††If this instruction addresses a port (

Seite 277

8XC251SA, SB, SP, SQ USER’S MANUALA-96MOVC A,@A+<base–reg> Function: Move code byte Description: Loads the accumulator with a code byte or const

Seite 278 - Table A-28. Flag Symbols

A-97INSTRUCTION SET REFERENCEHex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: MOVC (A) ← ((A) + (DPTR)) MOVH DRk,#data16Functio

Seite 279

2-3ARCHITECTURAL OVERVIEW2.1 8XC251SA, SB, SP, SQ ARCHITECTUREFigure 2-1 is a functional block diagram of the 8XC251SA, SB, SP, SQ. The core, which is

Seite 280

8XC251SA, SB, SP, SQ USER’S MANUALA-98Example: Eight-bit register Rm contains 055H (01010101B) and the 16-bit register WRj contains 0FFFFH (11111111 1

Seite 281

A-99INSTRUCTION SET REFERENCEExample: The MCS 251 controller is operating in nonpage mode. An external 256-byte RAM using multiplexed address/data lin

Seite 282

8XC251SA, SB, SP, SQ USER’S MANUALA-100MOVX @Ri,A Binary Mode Source ModeBytes: 11States: 44Hex Code in: Binary Mode = [Encoding]Source Mode = [A5][En

Seite 283

A-101INSTRUCTION SET REFERENCEMUL <dest>,<src>Function: MultiplyDescription: Multiplies the unsigned integer in the source register with t

Seite 284

8XC251SA, SB, SP, SQ USER’S MANUALA-102MUL WRjd,WRjsBinary Mode Source ModeBytes: 32States: 12 11Hex Code in: Binary Mode = [A5][Encoding]Source Mode

Seite 285

A-103INSTRUCTION SET REFERENCENOP Function: No operation Description: Execution continues at the following instruction. Affects the PC register only.

Seite 286

8XC251SA, SB, SP, SQ USER’S MANUALA-104Example: The accumulator contains 0C3H (11000011B) and R0 contains 55H (01010101B). After executing the instruc

Seite 287

A-105INSTRUCTION SET REFERENCEHex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: ORL (A) ← (A) V #dataORL A,dir8Binary Mode Sourc

Seite 288

8XC251SA, SB, SP, SQ USER’S MANUALA-106Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: ORL (Rmd) ← (Rmd) V (Rms) ORL WRjd,

Seite 289

A-107INSTRUCTION SET REFERENCEORL Rm,dir8Binary Mode Source ModeBytes: 43States: 3† 2††If this instruction addresses a port (Px, x = 0–3), add 1 state

Seite 290

8XC251SA, SB, SP, SQ USER’S MANUAL2-4The 8XC251Sx has two power-saving modes. In idle mode, the CPU clock is stopped, whileclocks to the peripherals c

Seite 291

8XC251SA, SB, SP, SQ USER’S MANUALA-108[Encoding]Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: ORL (WRj) ← (WRj) V (dir1

Seite 292

A-109INSTRUCTION SET REFERENCEExample: Set the CY flag if and only if P1.0 = 1, ACC. 7 = 1, or OV = 0: MOV CY,P1.0 ;LOAD CARRY WITH INPUT

Seite 293

8XC251SA, SB, SP, SQ USER’S MANUALA-110ORL CY,/bitBinary Mode Source ModeBytes: 43States: 3† 2††If this instruction addresses a port (Px, x = 0–3), ad

Seite 294 - IF (A) < dir8

A-111INSTRUCTION SET REFERENCEHex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: POP (dir8) ← ((SP)) (SP) ← (SP) – 1 POP RmBinary

Seite 295

8XC251SA, SB, SP, SQ USER’S MANUALA-112PUSH <dest>Function: Push onto stack Description: Increments the stack pointer by one. The contents of th

Seite 296

A-113INSTRUCTION SET REFERENCEPUSH #data16Binary Mode Source ModeBytes: 54States: 65[Encoding]Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [

Seite 297

8XC251SA, SB, SP, SQ USER’S MANUALA-114PUSH DRkBinary Mode Source ModeBytes: 32States: 98Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encod

Seite 298

A-115INSTRUCTION SET REFERENCERETI Function: Return from interrupt Description: This instruction pops two or four bytes from the stack, depending on t

Seite 299

8XC251SA, SB, SP, SQ USER’S MANUALA-116Operation for INTR = 1:RETI(PC).15:8 ← ((SP))(SP) ← (SP) – 1 PC).7:0 ← ((SP)) (SP) ← (SP) – 1 (PC).23:16 ← ((SP

Seite 300

A-117INSTRUCTION SET REFERENCEExample: The accumulator contains 0C5H (11000101B) and the CY flag is clear. After executing the instruction RLC A the a

Seite 301

2-5ARCHITECTURAL OVERVIEW2.2.1 CPUFigure 2-2 is a functional block diagram of the CPU (central processor unit). The 8XC251Sxfetches instructions from

Seite 302

8XC251SA, SB, SP, SQ USER’S MANUALA-118RRC A Function: Rotate accumulator right through carry flag Description: Rotates the eight bits in the accumula

Seite 303

A-119INSTRUCTION SET REFERENCESETB bit51Binary Mode Source ModeBytes: 22States: 2† 2††If this instruction addresses a port (Px, x = 0–3), add 2 states

Seite 304

8XC251SA, SB, SP, SQ USER’S MANUALA-120Flags:Example: The label "RELADR" is assigned to an instruction at program memory location 0123H. The

Seite 305

A-121INSTRUCTION SET REFERENCEHex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: SLL(Rm).a+1 ← (Rm).a (Rm).0 ← 0 CY ← (Rm).7S

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8XC251SA, SB, SP, SQ USER’S MANUALA-122SRA WRjBinary Mode Source ModeBytes: 32States: 21Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encodi

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A-123INSTRUCTION SET REFERENCESRL WRjBinary Mode Source ModeBytes: 32States: 21Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operat

Seite 308

8XC251SA, SB, SP, SQ USER’S MANUALA-124Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: SUB(Rmd) ← (Rmd) – (Rms) SUB WRjd,W

Seite 309

A-125INSTRUCTION SET REFERENCE[Encoding]Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: SUB (WRj) ← (WRj) – #data16 SUB DR

Seite 310

8XC251SA, SB, SP, SQ USER’S MANUALA-126SUB Rm,dir16Binary Mode Source ModeBytes: 54States: 32[Encoding]Hex Code in: Binary Mode = [A5][Encoding]Source

Seite 311

A-127INSTRUCTION SET REFERENCE[Encoding]Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: SUB (Rm) ← (Rm) – ((DRk))SUBB A,&l

Seite 312

8XC251SA, SB, SP, SQ USER’S MANUAL2-62.2.2 Clock and Reset UnitThe timing source for the 8XC251Sx can be an external oscillator or an internal oscilla

Seite 313

8XC251SA, SB, SP, SQ USER’S MANUALA-128 Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: SUBB (A) ← (A) – (CY) – #dataSUBB A

Seite 314

A-129INSTRUCTION SET REFERENCESWAP A Function: Swap nibbles within the accumulator Description: Interchanges the low and high nibbles (4-bit fields) o

Seite 315

8XC251SA, SB, SP, SQ USER’S MANUALA-130Binary Mode Source ModeBytes: 21States (2 bytes): 11 10States (4 bytes): 16 15Hex Code in: Binary Mode = [A5][E

Seite 316

A-131INSTRUCTION SET REFERENCEXCH A,@RiBinary Mode Source ModeBytes: 12States: 45Hex Code in: Binary Mode = [Encoding]Source Mode = [A5][Encoding]Oper

Seite 317

8XC251SA, SB, SP, SQ USER’S MANUALA-132Binary Mode Source ModeBytes: 12States: 45Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operatio

Seite 318

A-133INSTRUCTION SET REFERENCE Hex Code in: Binary Mode = [Encoding]Source Mode = [Encoding]Operation: XRL (dir8) ← (dir8) ∀ (A) XRL dir8,#dataBina

Seite 319

8XC251SA, SB, SP, SQ USER’S MANUALA-134XRL A,@RiBinary Mode Source ModeBytes: 12States: 23Hex Code in: Binary Mode = [Encoding]Source Mode = [A5][Enco

Seite 320

A-135INSTRUCTION SET REFERENCEOperation: XRL (WRds) ← (WRjd) ∀ (WRjs) XRL Rm,#dataBinary Mode Source ModeBytes: 43States: 32Hex Code in: Binary Mode =

Seite 321

8XC251SA, SB, SP, SQ USER’S MANUALA-136Hex Code in: Binary Mode = [A5][Encoding]Source Mode = [Encoding]Operation: XRL (WRj) ← (WRj) ∀ (dir8)XRL Rm,di

Seite 322

A-137INSTRUCTION SET REFERENCEXRL Rm,@DrkBinary Mode Source ModeBytes: 43States: 43[Encoding]Hex Code In: Binary Mode = [A5][Encoding]Source Mode = [E

Seite 323

2-7ARCHITECTURAL OVERVIEW2.2.3 Interrupt HandlerThe interrupt handler can receive interrupt requests from eleven sources: seven maskable sourcesand th

Seite 325

BSignal Descriptions

Seite 327

B-1APPENDIX BSIGNAL DESCRIPTIONSThis appendix provides reference information for the external signals of the 8XC251Sx. pin as-signments are shown in F

Seite 328

8XC251SA, SB, SP, SQ USER’S MANUALB-2Table B-1. PLCC/DIP Pin Assignments Listed by Functional CategoryAddress & Data Input/OutputName PLCC DIP Na

Seite 329

B-3SIGNAL DESCRIPTIONS Figure B-2. 8XC251SA, SB, SP, SQ 40-pin PDIP and Ceramic DIP Packages Table B-2. Signal Descriptions Signal NameType D

Seite 330

8XC251SA, SB, SP, SQ USER’S MANUALB-4CEX2:0CEX3CEX4I/O Programmable Counter Array (PCA) Input/Output Pins. These are input signals for the PCA capture

Seite 331

B-5SIGNAL DESCRIPTIONSRST I Reset. Reset input to the chip. Holding this pin high for 64 oscillator periods while the oscillator is running resets the

Seite 332

8XC251SA, SB, SP, SQ USER’S MANUALB-6VSS2GND Secondary Ground 2. This ground is provided to reduce ground bounce and improve power supply bypassing. C

Seite 333

B-7SIGNAL DESCRIPTIONS Table B-3. Memory Signal Selections (RD1:0) RD1:0P1.7/CEX/A17/WCLKP3.7/RD#/A16/ PSEN# WR# Features0 0 A17 A16 Asserted f

Seite 334

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including in-fringement of any pate

Seite 335

8XC251SA, SB, SP, SQ USER’S MANUAL2-8The watchdog timer is a circuit that automatically resets the 8XC251Sx in the event of a hardwareor software upse

Seite 337

CRegisters

Seite 339

C-1APPENDIX CREGISTERSThis appendix is a reference source of information for the 8XC251Sx special function registers(SFRs) and the register file. The

Seite 340

8XC251SA, SB, SP, SQ USER’S MANUALC-2Table C-1. 8XC251SA, SB, SP, SQ SFR Map0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/FF8CH 00000000CCAP0HxxxxxxxxCCAP1HxxxxxxxxC

Seite 341

C-3REGISTERSTable C-2. Core SFRsMnemonic Name AddressACC†Accumulator S:E0HB†B Register S:F0HPSW Program Status Word S:D0HPSW1 Program Status Word 1 S

Seite 342

8XC251SA, SB, SP, SQ USER’S MANUALC-4Table C-4. Serial I/O SFRsMnemonic Name AddressSCON Serial Control S:98HSBUF Serial Data Buffer S:99HSADEN Slav

Seite 343

C-5REGISTERS Table C-6. Programmable Counter Array (PCA) SFRsMnemonic Name AddressCCON PCA Timer/Counter Control S:D8HCMOD PCA Timer/Counter Mod

Seite 344

8XC251SA, SB, SP, SQ USER’S MANUALC-6 Table C-7. Register File Mnemonic AddressR0 – R7 Four banks of 8 registers. Select bank 0-3 with bits RS1:0

Seite 345

C-7REGISTERS ACCAddress: E0HReset State: 0000 0000BAccumulator. ACC provides SFR access to the accumulator, which resides in the register fil

Seite 346

3Address Spaces

Seite 347

8XC251SA, SB, SP, SQ USER’S MANUALC-8 CCAPxH, CCAPxL (x = 0–4)Address: CCAP0H,L S:FAH, S:EAHCCAP1H,L S:FBH, S:EBHCCAP2H,L S:FCH, S:ECHCCAP3H,L

Seite 348

C-9REGISTERS CCAPMx (x = 0–4)Address: CCAPM0 S:DAHCCAPM1 S:DBHCCAPM2 S:DCHCCAPM3 S:DDHCCAPM4 S:DEHReset State: X000 0000BPCA Compare/Capture Modu

Seite 349

8XC251SA, SB, SP, SQ USER’S MANUALC-10 CCONAddress: S:D8HReset State: 00X0 0000BPCA Timer/Counter Control Register. Contains the run control

Seite 350

C-11REGISTERSCMODAddress: S:D9HReset State: 00XX X000BPCA Timer/Counter Mode Register. Contains bits for selecting the PCA timer/counter input, disabl

Seite 351

8XC251SA, SB, SP, SQ USER’S MANUALC-12 DPHAddress: S:83HReset State: 0000 0000BData Pointer High. DPH provides SFR access to register file locat

Seite 352

C-13REGISTERS DPXLAddress: S:84HReset State: 0000 0001BData Pointer Extended Low. DPXL provides SFR access to register file location 57 (also name

Seite 353

8XC251SA, SB, SP, SQ USER’S MANUALC-14 IE0Address: S:A8HReset State: 0000 0000BInterrupt Enable Register 0. IE0 contains two types of interrupt ena

Seite 354

C-15REGISTERS IPH0Address: S:B7HReset State: X000 0000BInterrupt Priority High Control Register 0. IPH0, together with IPL0, assigns each interrup

Seite 355

8XC251SA, SB, SP, SQ USER’S MANUALC-16 IPL0Address: S:B8HReset State: X000 0000BInterrupt Priority Low Control Register 0. IPL0, together with IPH

Seite 356

C-17REGISTERS P0Address: S:80HReset State: 1111 1111BPort 0. P0 is the SFR that contains data to be driven out from the port 0 pins. Read-modify-wr

Seite 358

8XC251SA, SB, SP, SQ USER’S MANUALC-18P2Address: S:A0HReset State: 1111 1111BPort 2. P2 is the SFR that contains data to be driven out from the port 2

Seite 359

C-19REGISTERSPCONAddress: S:87HReset State: 00XX 0000BPower Control Register. Contains the power off flag (POF) and bits for enabling the idle and pow

Seite 360

8XC251SA, SB, SP, SQ USER’S MANUALC-20 .PSWAddress: S:D0HReset State: 0000 0000BProgram Status Word. PSW contains bits that reflect the results of ope

Seite 361

C-21REGISTERS PSW1Address: S:D1HReset State: 0000 0000BProgram Status Word 1. PSW1 contains bits that reflect the results of operations and bi

Seite 362

8XC251SA, SB, SP, SQ USER’S MANUALC-22 SADDRAddress: S:A9HReset State: 0000 0000BSlave Individual Address Register. SADDR contains the device’s i

Seite 363

C-23REGISTERS SADENAddress: S:B9HReset State: 0000 0000BMask Byte Register. This register masks bits in the SADDR register to form the device’s

Seite 364

8XC251SA, SB, SP, SQ USER’S MANUALC-24SCONAddress: 98HReset State: 0000 0000BSerial Port Control Register. SCON contains serial I/O control and status

Seite 365

C-25REGISTERSSCONAddress: 98HReset State: 0000 0000BSerial Port Control Register. SCON contains serial I/O control and status bits, including the mode

Seite 366

8XC251SA, SB, SP, SQ USER’S MANUALC-26SPHAddress: S:BEHReset State: 0000 0000BStack Pointer High. SPH provides SFR access to location 62 in the regist

Seite 367

C-27REGISTERS T2CONAddress: S:C8HReset State: 0000 0000BTimer 2 Control Register. Contains the receive clock, transmit clock, and capture/reload

Seite 368

3-1CHAPTER 3ADDRESS SPACESMCS® 251 microcontrollers have three address spaces: a memory space, a special function reg-ister (SFR) space, and a registe

Seite 369

8XC251SA, SB, SP, SQ USER’S MANUALC-28 T2MODAddress: S:C9HReset State: XXXX XX00BTimer 2 Mode Control Register. Contains the timer 2 down count e

Seite 370

C-29REGISTERS TCONAddress: S:88HReset State: 0000 0000BTimer/Counter Control Register. Contains the overflow and external interrupt flags and the

Seite 371

8XC251SA, SB, SP, SQ USER’S MANUALC-30TMODAddress: S:89HReset State: 0000 0000BTimer/Counter Mode Control Register. Contains mode select, run control

Seite 372

C-31REGISTERS TH0, TL0Address: TH0 S:8CHTL0 S:8AHReset State: 0000 0000BTH0, TL0 Timer Registers. These registers operate in cascade to for

Seite 373 - ← (WRj).b

8XC251SA, SB, SP, SQ USER’S MANUALC-32 TH2, TL2Address: TH2 S:CDHTL2 S:CCHReset State: 0000 0000BTH2, TL2 Timer Registers. These registers ope

Seite 374

C-33REGISTERS WDTRSTAddress: S:A6HReset State: XXXX XXXXBWatchdog Timer Reset Register. Writing the two-byte sequence 1EH-E1H to the WDTRST regist

Seite 376

Glossary

Seite 378

Glossary-1GLOSSARYThis glossary defines acronyms, abbreviations, and terms that have special meaning in this man-ual. (Chapter 1, “Guide to this Manua

Seite 379

8XC251SA, SB, SP, SQ USER’S MANUAL3-2It is convenient to view the unsegmented, 16-Mbyte memory space as consisting of 256 64-Kbyteregions, numbered 00

Seite 380

8XC251SA, SB, SP, SQ USER’S MANUALGlossary-2big endien form Memory storage format in which the most significantbyte (MSB) of the word or double word i

Seite 381

Glossary-3GLOSSARYdeassert The term deassert refers to the act of making a signalinactive (disabled). The polarity (high/low) is definedby the signal

Seite 382

8XC251SA, SB, SP, SQ USER’S MANUALGlossary-4interrupt handler The module responsible for handling interrupts thatare to be serviced by user-written in

Seite 383

Glossary-5GLOSSARYnonpage mode Conventional method for accessing external memorywhere code fetches require a two-state bus cycle. Seealso page mode.np

Seite 384

8XC251SA, SB, SP, SQ USER’S MANUALGlossary-6set The term set refers to the value of a bit or the act ofgiving it a value. If a bit is set, its value i

Seite 385

Glossary-7GLOSSARYword A 16-bit unit of data. In memory, a word comprisestwo contiguous bytes.wraparound The result of interpreting an address whosehe

Seite 389

Index-1#0data16, A-3#1data16, A-3#datadefinition, A-3#data16, A-3#short, A-38XC251SA, SB, SP, SQ, 1-1block diagram, 2-2on-chip peripherals, 2-

Seite 390

3-3ADDRESS SPACESThe register file (registers R0–R7) comprises four switchable register banks, each having eightregisters. The 32 bytes required for t

Seite 391 - Signal Descriptions

8XC251SA, SB, SP, SQ USER’S MANUALIndex-2CJNE instruction, A-25Clock, 2-6external, 11-4, 11-5external source, 11-3idle and powerdown modes, 12-5i

Seite 392

INDEXIndex-3ECI, 7-1EJMP instruction, 5-15, A-24EMAP# bit, 3-9, 4-16Encryption, 14-2Encryption arraykey bytes, 14-8programming, 14-1, 14-8setup

Seite 393 - SIGNAL DESCRIPTIONS

8XC251SA, SB, SP, SQ USER’S MANUALIndex-4detection, 6-3edge-triggered, 6-4enable/disable, 6-5exiting idle mode, 12-5exiting powerdown mode, 12-6e

Seite 394

INDEXIndex-5NN flag, 5-9, 5-19Noise reduction, 11-2, 11-3, 11-5Nonpage modebus cycles, See External bus cycles, Nonpage modebus structure, 13-1conf

Seite 395

8XC251SA, SB, SP, SQ USER’S MANUALIndex-6Phone numbers, customer support, 1-7Pin conditions, 12-3Pinsunused inputs, 11-2Pipeline, 2-5POP instructi

Seite 396

INDEXIndex-7RETI instruction, 6-1, 6-14, 6-15, A-24Return instructions, 5-15RL instruction, A-17RLC instruction, A-17ROM (on-chip), 14-1verifying

Seite 397

8XC251SA, SB, SP, SQ USER’S MANUALIndex-8T2, 7-1, 8-3T2CON, 3-17, 3-19, 8-1, 8-2, 8-10, 8-17, 10-13, C-2, C-4, C-27baud rate generator, 10-12T2EX,

Seite 398

INDEXIndex-9SFR (WDTRST), 3-19, C-4WCLK (Wait Clock) Output, 13-2WCON, 3-17, 13-11, C-2, C-3, C-32WDTRST, 3-17, 3-19, 8-2, 8-16, C-2, C-4, C-33Wor

Seite 400

8XC251SA, SB, SP, SQ USER’S MANUAL3-4Figure 3-3. Address Space Mappings MCS® 51 Architecture to MCS® 251 ArchitectureTable 3-1. Address Mappings Mem

Seite 401 - Registers

3-5ADDRESS SPACESThe 64-Kbyte external data memory for MCS 51 microcontrollers is mapped into the memoryregion specified by bits 16–23 of the data poi

Seite 402

8XC251SA, SB, SP, SQ USER’S MANUAL3-6 Figure 3-4. 8XC251SA, SB, SP, SQ Address Space A4385-0101:FFFFHFE:FFFFHFF:FFFFH01:0000HFE:0000HFF:0000HMemo

Seite 403 - REGISTERS

3-7ADDRESS SPACES Figure 3-5. Hardware Implementation of the 8XC251SA, SB, SP, SQ Address SpaceA4382-0201:FFFFHFE:FFFFHFF:FFF7H01:0000HFE:0000HFF:

Seite 404

iiiCONTENTSCHAPTER 1GUIDE TO THIS MANUAL1.1 MANUAL CONTENTS ...

Seite 405 - Table C-3. I/O Port SFRs

8XC251SA, SB, SP, SQ USER’S MANUAL3-8Locations FF:FFF8H–FF:FFFFH are reserved for the configuration array (see Chapter 4, “DeviceConfiguration”). The

Seite 406 - Table C-4. Serial I/O SFRs

3-9ADDRESS SPACESNOTEIf your program executes exclusively from on-chip ROM/OTPROM/EPROM (not from external memory), beware of executing code from the

Seite 407

8XC251SA, SB, SP, SQ USER’S MANUAL3-103.2.3 External MemoryRegions 01:, FE:, and portions of regions 00: and FF: of the memory space are implemented a

Seite 408 - Table C-7. Register File

3-11ADDRESS SPACES Figure 3-6. The Register File A4099-01DR4DR0DR12DR81514131211109823222120191817163130292827262524Locations 32-55 are Reserved

Seite 409

8XC251SA, SB, SP, SQ USER’S MANUAL3-12Register file locations 0–7 actually consist of four switchable banks of eight registers each, as il-lustrated i

Seite 410

3-13ADDRESS SPACES3.3.1 Byte, Word, and Dword RegistersDepending on its location in the register file, a register is addressable as a byte, a word, an

Seite 411

8XC251SA, SB, SP, SQ USER’S MANUAL3-14Instructions in the MCS 51 architecture use the accumulator as the primary register for datamoves and calculatio

Seite 412

3-15ADDRESS SPACES3.3.2.2 Extended Data Pointer, DPXDword register DR56 is the extended data pointer, DPX (Figure 3-8). The lower three bytes ofDPX (D

Seite 413

8XC251SA, SB, SP, SQ USER’S MANUAL3-163.4 SPECIAL FUNCTION REGISTERS (SFRS)The special function registers (SFRs) reside in their associated on-chip pe

Seite 414

3-17ADDRESS SPACESTable 3-5. 8XC251SA, SB, SP, SQ SFR Map and Reset Values0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/FF8CH 00000000CCAP0HxxxxxxxxCCAP1HxxxxxxxxCCA

Seite 415

8XC251SA, SB, SP, SQ USER’S MANUALiv3.3.2.3 Extended Stack Pointer, SPX ...3

Seite 416

8XC251SA, SB, SP, SQ USER’S MANUAL3-18The following tables list the mnemonics, names, and addresses of the SFRs:Table 3-6 — Core SFRsTable 3-7 — I/O P

Seite 417

3-19ADDRESS SPACESTable 3-8. Serial I/O SFRsMnemonic Name AddressSCON Serial Control S:98HSBUF Serial Data Buffer S:99HSADEN Slave Address Mask S:B9

Seite 418

8XC251SA, SB, SP, SQ USER’S MANUAL3-20CL PCA Timer/Counter Low Byte S:E9HCH PCA Timer/Counter High Byte S:F9HCCAP0L PCA Compare/Capture Module 0 Lo

Seite 419

4DeviceConfiguration

Seite 421

4-1CHAPTER 4DEVICE CONFIGURATIONThe 8XC251Sx provides user design flexibility by configuring certain operating features at de-vice reset. These featur

Seite 422

8XC251SA, SB, SP, SQ USER’S MANUAL4-2For ROM/OTPROM/EPROM devices, user configuration bytes UCONFIG0 and UCONFIG1can be programmed at the factory or o

Seite 423

4-3DEVICE CONFIGURATION Figure 4-2. Configuration Array (External) A4236-011FF9H1FF8H8 Kbytes3FF9H3FF8H16 Kbytes7FF9H7FF8H32 KbytesFFF9HFFF8H64 Kby

Seite 424

8XC251SA, SB, SP, SQ USER’S MANUAL4-4 4.3 THE CONFIGURATION BITSThis section provides a brief description of the configuration bits contained in

Seite 425

4-5DEVICE CONFIGURATION4.4 CONFIGURATION BYTE LOCATION SELECTOR (UCON)The Configuration Byte Location Selector (UCON) applies only to OTPROM and EPROM

Seite 426

CONTENTSv5.4 BIT INSTRUCTIONS ... 5-115.4.1 Bit Addres

Seite 427

8XC251SA, SB, SP, SQ USER’S MANUAL4-6 Figure 4-3. Configuration Byte UCONFIG0UCONFIG0(1), (3)Address:FF:FFF8H (2)7 0UCON WSA1# WSA0# XALE# RD1 RD

Seite 428

4-7DEVICE CONFIGURATION Figure 4-4. Configuration Byte UCONFIG1UCONFIG1 (1), (3)Address:FF:FFF9H (2)7 0— — — INTR WSB WSB1# WSB0# EMAP#Bit Number

Seite 429

8XC251SA, SB, SP, SQ USER’S MANUAL4-8 4.5 CONFIGURING THE EXTERNAL MEMORY INTERFACEThis section describes the configuration options that affect th

Seite 430

4-9DEVICE CONFIGURATION4.5.2 Configuration Bits RD1:0The RD1:0 configuration bits (UCONFIG0.3:2) determine the number of external address signalsand t

Seite 431

8XC251SA, SB, SP, SQ USER’S MANUAL4-10This selection provides a 128-Kbyte external address space. The advantage of this selection, incomparison with t

Seite 432

4-11DEVICE CONFIGURATION Figure 4-6. Internal/External Address Mapping (RD1:0 = 10 and 11) FF:01:PSEN#RD#, WR#A4217-02FF:FE:01:00:RD1:0 = 1016 ex

Seite 433

8XC251SA, SB, SP, SQ USER’S MANUAL4-124.5.2.3 RD1:0 = 10 (16 External Address Bits) For RD1:0 = 10, the 16 external address bits (A15:0 on ports P0 an

Seite 434

4-13DEVICE CONFIGURATION4.5.3.3 Configuration Bit XALE#Clearing XALE# (UCONFIG0.4) extends the time ALE is asserted from TOSC to 3TOSC. This ac-commod

Seite 435

8XC251SA, SB, SP, SQ USER’S MANUAL4-14Figure 4-7 shows the opcode map for binary mode. Area I (columns 1 through 5 in Table A-6 onpage A-4) and area I

Seite 436

4-15DEVICE CONFIGURATIONFigure 4-7. Binary Mode Opcode Map Figure 4-8. Source Mode Opcode Map A4131-01I II0H 5H FH6H0HFHMCS® 51ArchitectureMCS 51A

Seite 437 - Glossary

8XC251SA, SB, SP, SQ USER’S MANUALvi8.2 TIMER/COUNTER OPERATION... 8-1

Seite 438

8XC251SA, SB, SP, SQ USER’S MANUAL4-164.7 MAPPING ON-CHIP CODE MEMORY TO DATA MEMORY (EMAP#)For devices with 16 Kbytes of on-chip code memory (87C251S

Seite 441 - Glossary-3

5-1CHAPTER 5PROGRAMMINGThe instruction set for the MCS® 251 architecture is a superset of the instruction set for theMCS®51 architecture. This chapter

Seite 442 - Glossary-4

8XC251SA, SB, SP, SQ USER’S MANUAL5-25.2.1 Data TypesTable 5-1 lists the data types that are addressed by the instruction set. Words or dwords (double

Seite 443 - Glossary-5

5-3PROGRAMMING Figure 5-1. Word and Double-word Storage in Big Endien FormInstructions in the MCS 51 architecture use 80H–FFH as addresses for bot

Seite 444 - Glossary-6

8XC251SA, SB, SP, SQ USER’S MANUAL5-45.2.4 Addressing ModesThe MCS 251 architecture supports the following addressing modes:• register addressing: The

Seite 445 - Glossary-7

5-5PROGRAMMING5.3.1.1 Register AddressingBoth architectures address registers directly.• MCS 251 architecture. In the register addressing mode, the op

Seite 446

8XC251SA, SB, SP, SQ USER’S MANUAL5-65.3.1.4 IndirectIn arithmetic and logical instructions that use indirect addressing, the source operand is always

Seite 447

5-7PROGRAMMING Table 5-4. Addressing Modes for Data Instructions in the MCS® 251 ArchitectureMode Address Range of OperandAssembly Language Notat

Seite 448

CONTENTSvii10.2 MODES OF OPERATION... 10-410.2.1 Synchronous

Seite 449

8XC251SA, SB, SP, SQ USER’S MANUAL5-85.3.1.5 Displacement Several move instructions use displacement addressing to move bytes or words from a source t

Seite 450

5-9PROGRAMMINGThe MCS 251 architecture provides the MUL (multiply) and DIV (divide) instructions for un-signed 8-bit and 16-bit data (Table A-22 on pa

Seite 451

8XC251SA, SB, SP, SQ USER’S MANUAL5-105.3.4 Data Transfer InstructionsData transfer instructions copy data from one register or memory location to ano

Seite 452

5-11PROGRAMMING5.4 BIT INSTRUCTIONSA bit instruction addresses a specific bit in a memory location or SFR. There are four categoriesof bit instruction

Seite 453

8XC251SA, SB, SP, SQ USER’S MANUAL5-12Table 5-7 lists the addressing modes for bit instructions and Table A-26 on page A-23 summarizesthe bit instruct

Seite 454

5-13PROGRAMMING5.5.1 Addressing Modes for Control InstructionsTable 5-8 lists the addressing modes for the control instructions.• Relative addressing:

Seite 455

8XC251SA, SB, SP, SQ USER’S MANUAL5-145.5.2 Conditional JumpsThe MCS 251 architecture supports bit-conditional jumps, compare-conditional jumps, andju

Seite 456

5-15PROGRAMMING5.5.3 Unconditional JumpsThere are five unconditional jumps. NOP and SJMP jump to addresses relative to the programcounter. AJMP, LJMP,

Seite 457

8XC251SA, SB, SP, SQ USER’S MANUAL5-16RETI (Return from Interrupt) provides a return from an interrupt service routine. The operationof RETI depends o

Seite 458

5-17PROGRAMMINGTable 5-10. The Effects of Instructions on the PSW and PSW1 FlagsInstruction Type InstructionFlags Affected (1), (5)CY OV AC (2) N ZAr

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