Intel PXA255 Bedienungsanleitung Seite 1

Intel® PXA255 ProcessorDeveloper’s ManualJanuary, 2004Order Number: 278693-002

x Intel® PXA255 Processor Developer’s Manual Contents12.6 UDC Register Definitions...

3-38 Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager3.6.3 Oscillator Configuration Register (OSCC)The OSCC, shown in Table 3-22,

Intel® PXA255 Processor Developer’s Manual 3-39 Clocks and Power Manager3.7.1 Core Clock Configuration Register (CCLKCFG)The CCLKCFG register (CP14 re

3-40 Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager3.7.2 Power Mode Register (PWRMODE)The PWRMODE register (CP14, register 7), s

Intel® PXA255 Processor Developer’s Manual 3-41 Clocks and Power Manager3.8.3 Driving the Crystal Pins from an External Clock SourceThe information in

3-42 Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager.Table 3-27. Power Manager Register Summary Address Name Description0x40F0_00

Intel® PXA255 Processor Developer’s Manual 4-1System Integration Unit 4This chapter describes the System Integration Unit (SIU) for the PXA255 process

4-2 Intel® PXA255 Processor Developer’s Manual System Integration UnitWhen the processor enters sleep mode, the contents of the Power Manager Sleep S

Intel® PXA255 Processor Developer’s Manual 4-3 System Integration UnitFor more information on alternate functions, refer to the Source Unit column in

4-4 Intel® PXA255 Processor Developer’s Manual System Integration UnitGP33 nCS[5] ALT_FN_2_OUT 10 Memory Controller Active low chip select 5GP34FFRXD

Intel® PXA255 Processor Developer’s Manual 4-5 System Integration UnitGP54 MMCCLK ALT_FN_1_OUT 01Multimedia Card (MMC) ControllerMMC ClockGP54 nPSKTSE

Intel® PXA255 Processor Developer’s Manual xi Contents14.3 Controller Operation ...

4-6 Intel® PXA255 Processor Developer’s Manual System Integration Unit4.1.3 GPIO Register DefinitionsThere are twenty-seven 32-bit registers within t

Intel® PXA255 Processor Developer’s Manual 4-7 System Integration UnitNote: Write zeros to all reserved bits and ignore all reads from these bits.Note

4-8 Intel® PXA255 Processor Developer’s Manual System Integration UnitThis is read/write register. Ignore reads from reserved bits. Write zeros to re

Intel® PXA255 Processor Developer’s Manual 4-9 System Integration Unit4.1.3.3 GPIO Pin Output Set Registers (GPSR0, GPSR1, and GPSR2) and Pin Output C

4-10 Intel® PXA255 Processor Developer’s Manual System Integration UnitWhen a GPIO is configured as an output, the state of the pin can be controlled

Intel® PXA255 Processor Developer’s Manual 4-11 System Integration UnitTable 4-11. GPSR2 Bit Definitions Physical Address0x40E0_0020GPSR2 System Integ

4-12 Intel® PXA255 Processor Developer’s Manual System Integration Unit4.1.3.4 GPIO Rising Edge Detect Enable Registers (GRER0, GRER1, GRER2) and Fal

Intel® PXA255 Processor Developer’s Manual 4-13 System Integration UnitTable 4-15. GRER0 Bit Definitions Physical Address0x40E0_0030GRER0 System Integ

4-14 Intel® PXA255 Processor Developer’s Manual System Integration UnitTable 4-18. GFER0 Bit Definitions Physical Address0x40E0_003CGFER0 System Inte

Intel® PXA255 Processor Developer’s Manual 4-15 System Integration Unit4.1.3.5 GPIO Edge Detect Status Register (GEDR0, GEDR1, GEDR2)GEDR0, GEDR1, GED

xii Intel® PXA255 Processor Developer’s Manual Contents15.5 MMC Controller Registers ...

4-16 Intel® PXA255 Processor Developer’s Manual System Integration Unit4.1.3.6 GPIO Alternate Function Register (GAFR0_L, GAFR0_U, GAFR1_L, GAFR1_U,

Intel® PXA255 Processor Developer’s Manual 4-17 System Integration UnitCaution: Configuring a GPIO to map to an alternate function that is not availab

4-18 Intel® PXA255 Processor Developer’s Manual System Integration UnitTable 4-26. GAFR1_L Bit Definitions Physical Address0x40E0_005CGAFR1_L System

Intel® PXA255 Processor Developer’s Manual 4-19 System Integration Unit4.1.3.7 Example Procedure for Configuring the Alternate Function RegistersIn th

4-20 Intel® PXA255 Processor Developer’s Manual System Integration Unit• GPIO[1] is an input configured to alternate function 1 (ALT_FN_1_IN)• GPIO[5

Intel® PXA255 Processor Developer’s Manual 4-21 System Integration Unit— Interrupt Controller FIQ Pending Register (ICFP) – contains the interrupts fr

4-22 Intel® PXA255 Processor Developer’s Manual System Integration UnitAfter a reset, the FIQ and IRQ interrupts are disabled within the CPU, and the

Intel® PXA255 Processor Developer’s Manual 4-23 System Integration Unit4.2.2.3 Interrupt Controller Control Register (ICCR)The ICCR, shown in Table 4-

4-24 Intel® PXA255 Processor Developer’s Manual System Integration Unit4.2.2.4 Interrupt Controller IRQ Pending Register (ICIP) and FIQ Pending Regis

Intel® PXA255 Processor Developer’s Manual 4-25 System Integration Unit4.2.2.5 Interrupt Controller Pending Register (ICPR)The ICPR, shown in Table 4-

Intel® PXA255 Processor Developer’s Manual xiii Contents17.4.4 Auto-Baud-Rate Detection...

4-26 Intel® PXA255 Processor Developer’s Manual System Integration Unit<22> IS22FFUART Transmit/Receive/Error Interrupt Pending0 – Interrupt NO

Intel® PXA255 Processor Developer’s Manual 4-27 System Integration Unit<9> IS9GPIO[1] Edge Detect Interrupt Pending0 – Interrupt NOT pending due

4-28 Intel® PXA255 Processor Developer’s Manual System Integration UnitSeveral units have more than one source per interrupt signal. When an interrup

Intel® PXA255 Processor Developer’s Manual 4-29 System Integration UnitIn addition to the RCNR, the RTC incorporates a 32-bit, RTC Alarm register (RTA

4-30 Intel® PXA255 Processor Developer’s Manual System Integration Unit4.3.2.2 RTC Alarm Register (RTAR)The RTAR, Table 4-38, is a 32-bit register. T

Intel® PXA255 Processor Developer’s Manual 4-31 System Integration Unit4.3.2.3 RTC Counter Register (RCNR)The RCNR, shown in Table 4-39, is a read/wri

4-32 Intel® PXA255 Processor Developer’s Manual System Integration Unit4.3.3 Trim ProcedureThe HZ clock driving the RTC is generated by dividing the

Intel® PXA255 Processor Developer’s Manual 4-33 System Integration Unit4.3.3.2 RTTR Value CalculationsAfter the true frequency of the oscillator is kn

4-34 Intel® PXA255 Processor Developer’s Manual System Integration Unitbring the HZ output frequency down to the proper value. Since the trimming pro

Intel® PXA255 Processor Developer’s Manual 4-35 System Integration Unitalso routed to the interrupt controller where they can be programmed to cause a

xiv Intel® PXA255 Processor Developer’s Manual Contents6-15 Flash Memory Reset Logic if Watchdog Reset is Not Necessary ...

4-36 Intel® PXA255 Processor Developer’s Manual System Integration Unit4.4.2.2 OS Timer Interrupt Enable Register (OIER)The OIER, shown in Table 4-42

Intel® PXA255 Processor Developer’s Manual 4-37 System Integration Unit4.4.2.3 OS Timer Watchdog Match Enable Register (OWER)The OWER, shown in Table

4-38 Intel® PXA255 Processor Developer’s Manual System Integration Unit4.5 Pulse Width ModulatorUse the Pulse Width Modulator (PWM) to generate as ma

Intel® PXA255 Processor Developer’s Manual 4-39 System Integration Unit4.5.1.1 InterdependenciesThe PWM unit is clocked off the 3.6864 MHz oscillator

4-40 Intel® PXA255 Processor Developer’s Manual System Integration Unitcomparator contains PWM_PERVALn[PV] and clears the PWM_OUT signal low when PWM

Intel® PXA255 Processor Developer’s Manual 4-41 System Integration Unit4.5.2.2 PWM Duty Cycle Registers (PWM_DUTYn)The PWM_DUTYn, shown in Table 4-47,

4-42 Intel® PXA255 Processor Developer’s Manual System Integration Unit4.5.2.3 PWM Period Control Register (PWM_PERVALn)The PWM_PERVALn, shown in Tab

Intel® PXA255 Processor Developer’s Manual 4-43 System Integration Unit4.5.3 Pulse Width Modulator Output Wave ExampleFigure 4-4 is an example of the

4-44 Intel® PXA255 Processor Developer’s Manual System Integration Unit4.6 System Integration Unit Register Summary4.6.1 GPIO Register LocationsTable

Intel® PXA255 Processor Developer’s Manual 4-45 System Integration Unit4.6.2 Interrupt Controller Register Locations Table 4-50 shows the registers as

Intel® PXA255 Processor Developer’s Manual xv Contents9-3 START and STOP Conditions ...

4-46 Intel® PXA255 Processor Developer’s Manual System Integration Unit4.6.5 Pulse Width Modulator Register LocationsTable 4-53 shows the registers a

Intel® PXA255 Processor Developer’s Manual 5-1DMA Controller 5This chapter describes the on-chip DMA controller (DMAC) for the PXA255 processor. The D

5-2 Intel® PXA255 Processor Developer’s Manual DMA Controller5.1.1 DMAC ChannelsThe DMAC has 16 channels, each controlled by four 32-bit registers. E

Intel® PXA255 Processor Developer’s Manual 5-3 DMA Controllermust remain deasserted for at least four MEMCLKs. The DMAC registers the transition from

5-4 Intel® PXA255 Processor Developer’s Manual DMA ControllerIf all channels request data transfers, the Sets are prioritized in following order: • S

Intel® PXA255 Processor Developer’s Manual 5-5 DMA Controllerstate is incremented, wrapping around from state machine state seven back to state machin

5-6 Intel® PXA255 Processor Developer’s Manual DMA Controller7. The channel waits for the next request or continues with the data transfer until the

Intel® PXA255 Processor Developer’s Manual 5-7 DMA Controllera. Word [0] -> DDADRx register and a single flag bit. Points to the next four-word des

5-8 Intel® PXA255 Processor Developer’s Manual DMA Controller5.1.4.3 Servicing an InterruptIf software receives an interrupt caused by a successful d

Intel® PXA255 Processor Developer’s Manual 5-9 DMA Controller• Wait for Request: Channel is waiting for a request before it starts to transfer the dat

xvi Intel® PXA255 Processor Developer’s Manual Contents16-8 National Semiconductor Microwire* Frame Protocol (single transfers) ...

5-10 Intel® PXA255 Processor Developer’s Manual DMA Controller5.1.8 Trailing BytesThe DMA normally transfers bytes equal to the transaction size spec

Intel® PXA255 Processor Developer’s Manual 5-11 DMA Controller• Internal Peripheral to Memory Transfers: Most peripherals do not send a request for tr

5-12 Intel® PXA255 Processor Developer’s Manual DMA Controller5.2.1.1 Using Flow-Through DMA Read Cycles to Service Internal PeripheralsA flow-throug

Intel® PXA255 Processor Developer’s Manual 5-13 DMA Controller5.2.2 Quick Reference for DMA ProgrammingUse Table 5-5 as a quick reference sheet for pr

5-14 Intel® PXA255 Processor Developer’s Manual DMA Controller5.2.3 Servicing Companion Chips and External PeripheralsCompanion chips and external pe

Intel® PXA255 Processor Developer’s Manual 5-15 DMA Controller5.2.3.1 Using Flow-Through DMA Read Cycles to Service External PeripheralsA flow-through

5-16 Intel® PXA255 Processor Developer’s Manual DMA ControllerFor a flow-through DMA write to an external peripheral, use the following settings for

Intel® PXA255 Processor Developer’s Manual 5-17 DMA Controller5.3 DMAC RegistersThe section describes the DMAC registers.5.3.1 DMA Interrupt Register

5-18 Intel® PXA255 Processor Developer’s Manual DMA ControllerTable 5-7. DCSRx Bit Definitions (Sheet 1 of 2)Physical Address0x4000_0000 - 0x4000_003

Intel® PXA255 Processor Developer’s Manual 5-19 DMA Controller3STOPSTATEStop State (read-only).0 – channel is running1 – channel is in uninitialized o

Intel® PXA255 Processor Developer’s Manual xvii Contents3-26 Clocks Manager Register Summary ...

5-20 Intel® PXA255 Processor Developer’s Manual DMA Controller5.3.3 DMA Request to Channel Map Registers (DRCMRx)DRCMRx, shown in Table 5-8, map each

Intel® PXA255 Processor Developer’s Manual 5-21 DMA Controller 5.3.5 DMA Source Address RegistersDSADRx, shown in Table 5-10, are read only in the Des

5-22 Intel® PXA255 Processor Developer’s Manual DMA Controller5.3.6 DMA Target Address Registers (DTADRx)To software, DTADRx (Table 5-11) is read onl

Intel® PXA255 Processor Developer’s Manual 5-23 DMA Controller5.3.7 DMA Command Registers (DCMDx)For software, DCMDx (Table 5-12) is read only in Desc

5-24 Intel® PXA255 Processor Developer’s Manual DMA ControllerTable 5-12. DCMDx Bit Definitions (Sheet 1 of 2)0x4000_02xC DMA Command Register (DCMDx

Intel® PXA255 Processor Developer’s Manual 5-25 DMA Controller18 ENDIANDevice Endian-ness. (read / write).0 – Byte ordering is little endian1 – reserv

5-26 Intel® PXA255 Processor Developer’s Manual DMA Controller5.4 ExamplesThis section contains examples that show how to:• Set up and start a channe

Intel® PXA255 Processor Developer’s Manual 5-27 DMA Controller3. In memory, create the descriptor to be added and set its stop bit to a 1.4. In the me

5-28 Intel® PXA255 Processor Developer’s Manual DMA ControllerWhen the external device has data to transfer, it makes a DMA request in the standard w

Intel® PXA255 Processor Developer’s Manual 5-29 DMA Controller0x4000_0110 DRCMR4Request to Channel Map Register for BTUART receive Request0x4000_0114

xviii Intel® PXA255 Processor Developer’s Manual Contents4-49 GPIO Register Addresses ...

5-30 Intel® PXA255 Processor Developer’s Manual DMA Controller0x4000_0174 DRCMR29 reserved0x4000_0178 DRCMR30Request to Channel Map Register for USB

Intel® PXA255 Processor Developer’s Manual 5-31 DMA Controller0x4000_0258 DTADR5 DMA Target Address Register channel 50x4000_025C DCMD5 DMA Command Ad

5-32 Intel® PXA255 Processor Developer’s Manual DMA Controller0x4000_02EC DCMD14 DMA Command Address Register channel 140x4000_02F0 DDADR15 DMA Descr

Intel® PXA255 Processor Developer’s Manual 6-1Memory Controller 6This chapter describes the external memory interface structures and memory-related re

6-2 Intel® PXA255 Processor Developer’s Manual Memory Controller6.2 Functional DescriptionThe processor has three different memory spaces: SDRAM, Sta

Intel® PXA255 Processor Developer’s Manual 6-3 Memory Controllerpartition pairs: the 0/1 pair and the 2/3 pair. The partitions in a pair must be ident

6-4 Intel® PXA255 Processor Developer’s Manual Memory Controllerasserted on writes to Variable Latency I/O devices, and nWE is asserted on writes to

Intel® PXA255 Processor Developer’s Manual 6-5 Memory ControllerFigure 6-2. SDRAM Memory System Example4Mx16SDRAMnCSnRASnCASCLKCKEnWEaddr(11:0)BA(1:0)

6-6 Intel® PXA255 Processor Developer’s Manual Memory ControllerFigure 6-3 shows an alternate memory configuration. This system uses 2M x 16 SMROM de

Intel® PXA255 Processor Developer’s Manual 6-7 Memory Controller6.4 Memory AccessesIf a memory access is followed by an idle bus period, the control s

Intel® PXA255 Processor Developer’s Manual xix Contents6-33 Attribute Memory Space Write Commands ...

6-8 Intel® PXA255 Processor Developer’s Manual Memory Controller6.4.1 Reads and WritesDQM[3:0] are data masking bits. When asserted (high), the corre

Intel® PXA255 Processor Developer’s Manual 6-9 Memory ControllerThis is a read/write register. Ignore reads from reserved bits. Write zeros to reserve

6-10 Intel® PXA255 Processor Developer’s Manual Memory Controller9:8 DTC0[1:0]Timing Category for SDRAM pair 0/1.00 - tRP = 2 clks, CL = 2, tRCD = 1

Intel® PXA255 Processor Developer’s Manual 6-11 Memory Controller20:19 DCAC2[1:0]Number of Column Address bits for partition pair 2/300 – 8 column add

6-12 Intel® PXA255 Processor Developer’s Manual Memory Controller6.5.2 SDRAM Mode Register Set Configuration Register (MDMRS)The MDMRS, shown in Tabl

Intel® PXA255 Processor Developer’s Manual 6-13 Memory Controller6.5.2.1 Low-Power SDRAM Mode Register Set Configuration RegisterThe Low-Power SDRAM M

6-14 Intel® PXA255 Processor Developer’s Manual Memory Controller6.5.3 SDRAM MDREFR Register (MDREFR)MDREFR, shown in Table 6-5, is a read/write regi

Intel® PXA255 Processor Developer’s Manual 6-15 Memory ControllerThis is a read/write register. Ignore reads from reserved bits. Write zeros to reserv

6-16 Intel® PXA255 Processor Developer’s Manual Memory Controller18 K2RUNSDRAM Clock Pin 2 (SDCLK<2>) Run Control/Status0 – SDCLK2 disabled1 –

Intel® PXA255 Processor Developer’s Manual 6-17 Memory Controller6.5.4 Fixed-Delay or Return-Clock Data LatchingThe Return-clock data latching works i

ii Intel® PXA255 Processor Developer’s ManualINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLI

xx Intel® PXA255 Processor Developer’s Manual Contents10-5 DLL Bit Definitions...

6-18 Intel® PXA255 Processor Developer’s Manual Memory Controller6.5.5 SDRAM Memory OptionsThe Dynamic Memory interface supports up to four partition

Intel® PXA255 Processor Developer’s Manual 6-19 Memory ControllerTable 6-4 shows how the SDRAM row and column addresses are mapped to the internal SDR

6-20 Intel® PXA255 Processor Developer’s Manual Memory Controller1x12x10x16 23 22 21 20 19 18 17 16 15 14 13 12 11 23 ‘0’ 10 9 8 7 6543211x12x11x32 2

Intel® PXA255 Processor Developer’s Manual 6-21 Memory Controller2x13x8x32 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 24 23 ‘0’ 987654322x13x8x16 23

6-22 Intel® PXA255 Processor Developer’s Manual Memory Controller1x12x10x16 22 21 20 19 18 17 16 15 14 13 12 11 10 21 ‘0’ 23 9 8 7 6 5 4 3 2 11x12x11

Intel® PXA255 Processor Developer’s Manual 6-23 Memory ControllerUse the information below to connect the processor to the SDRAM devices. Some of the

6-24 Intel® PXA255 Processor Developer’s Manual Memory Controller1x12x9x16 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A01x12x10x32 BA0 A11 A10 A9 A8 A7 A

Intel® PXA255 Processor Developer’s Manual 6-25 Memory Controller2x12x11x32 BA1BA0A11A10A9A8A7A6A5A4A3A2A1A02x12x11x16 BA1BA0A11A10A9A8A7A6A5A4A3A2A1A

6-26 Intel® PXA255 Processor Developer’s Manual Memory Controller1x12x9x16 A11BA0A10A9A8A7A6A5A4A3A2A1A01x12x10x32 A11 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A

Intel® PXA255 Processor Developer’s Manual 6-27 Memory Controller6.5.6 SDRAM Command OverviewThe processor accesses SDRAM with the following subset of

Intel® PXA255 Processor Developer’s Manual xxi Contents12-26 UBCR2/4/7/9/12/14 Bit Definitions...

6-28 Intel® PXA255 Processor Developer’s Manual Memory ControllerThe programmable opcode for address bits MA<24:17> used during the mode-regist

Intel® PXA255 Processor Developer’s Manual 6-29 Memory ControllerFigure 6-5. Basic SDRAM Timing ParametersFigure 6-6. SDRAM_Read_diffbank_diffrowCLCLt

6-30 Intel® PXA255 Processor Developer’s Manual Memory ControllerFigure 6-7. SDRAM_read_samebank_diffrowFigure 6-8. SDRAM_read_samebank_samerowCLCLtR

Intel® PXA255 Processor Developer’s Manual 6-31 Memory ControllerFigure 6-9. SDRAM_writeFigure 6-10. SDRAM 4-Beat Read/ 4-Beat Write To Different Part

6-32 Intel® PXA255 Processor Developer’s Manual Memory Controller6.6 Synchronous Static Memory InterfaceThe synchronous static memory interface suppo

Intel® PXA255 Processor Developer’s Manual 6-33 Memory ControllerTable 6-13. SXCNFG Bit Definitions (Sheet 1 of 4)0x4800_001C SXCNFG Memory Controller

6-34 Intel® PXA255 Processor Developer’s Manual Memory Controller20:18 SXCL2CAS Latency for SX Memory partition pair 2/3Number of external SDCLK cycl

Intel® PXA255 Processor Developer’s Manual 6-35 Memory Controller11:10 SXCA0SX Memory column address bit count for partition pair 0/100 – 7 column add

6-36 Intel® PXA255 Processor Developer’s Manual Memory Controller6.6.1.1 SMROM Memory OptionsTable 6-15 shows the possible external-to-internal addre

Intel® PXA255 Processor Developer’s Manual 6-37 Memory Controller6.6.2 Synchronous Static Memory Mode Register Set Configuration Register (SXMRS)On po

15-7 MMC_CLK Bit Definitions ...15-2515-8 MMC_SPI B

6-38 Intel® PXA255 Processor Developer’s Manual Memory ControllerSXCNFG[RL] fields must match any CAS latencies and RAS latencies programmed in this

Intel® PXA255 Processor Developer’s Manual 6-39 Memory Controller6.6.4 Non-SDRAM Timing SXMEM OperationNon-SDRAM Timing Synchronous Flash operation re

6-40 Intel® PXA255 Processor Developer’s Manual Memory ControllerTable 6-18 shows sample frequency configurations for programming non-SDRAM Timing Fa

Intel® PXA255 Processor Developer’s Manual 6-41 Memory Controller6.6.4.1 Non-SDRAM Timing Flash Read Timing DiagramFigure 6-12 shows the burst-of-eigh

6-42 Intel® PXA255 Processor Developer’s Manual Memory ControllerFor divide-by-two mode, the following timing parameters apply:• nADV assert time = 3

Intel® PXA255 Processor Developer’s Manual 6-43 Memory Controller• Non-burst ROM or Flash memory• Burst ROM or Flash• SRAM • SRAM-like variable latenc

6-44 Intel® PXA255 Processor Developer’s Manual Memory ControllerThe RT fields in the MSCx registers specify the type of memory: • Non-burst ROM or F

Intel® PXA255 Processor Developer’s Manual 6-45 Memory ControllerTable 6-21. 32-Bit Byte Address Bits MA[1:0] for Reads Based on DQM[3:0] DQM[3:0] MA[

6-46 Intel® PXA255 Processor Developer’s Manual Memory Controller6.7.3 Asynchronous Static Memory Control Registers (MSCx)The MSCx, shown in Table 6-

Intel® PXA255 Processor Developer’s Manual 6-47 Memory ControllerTable 6-24. MSC0/1/2 Bit Definitions (Sheet 1 of 3)0x4800_00080x4800_000C0x4800_0010M

Intel® PXA255 Processor Developer’s Manual xxiii ContentsRevision HistoryDate Revision DescriptionMarch 2003 -001 Initial releaseJanuary 2004 -002Repl

6-48 Intel® PXA255 Processor Developer’s Manual Memory Controller7:4 R/W RDFx<3:0>ROM delay first access.RDF programmed RDF value interpreted0-

Intel® PXA255 Processor Developer’s Manual 6-49 Memory Controller2:0 R/W RTx<2:0>ROM type000 - Nonburst ROM or Flash Memory001 - SRAM 010 - Burs

6-50 Intel® PXA255 Processor Developer’s Manual Memory ControllerTable 6-25 provides a comparison of supported Asynchronous Static Memory types.6.7.4

Intel® PXA255 Processor Developer’s Manual 6-51 Memory Controller6.7.4.1 ROM Timing Diagrams and ParametersFigure 6-17, Figure 6-18, and Figure 6-19 s

6-52 Intel® PXA255 Processor Developer’s Manual Memory ControllerFigure 6-18. Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash (MSC0[RDF]

Intel® PXA255 Processor Developer’s Manual 6-53 Memory Controller6.7.5 SRAM Interface OverviewThe processor provides a 16-bit or 32-bit asynchronous S

6-54 Intel® PXA255 Processor Developer’s Manual Memory ControllerFor writes to SRAM, if all byte enables are turned off (masking out the data, DQM =

Intel® PXA255 Processor Developer’s Manual 6-55 Memory Controller6.7.6 Variable Latency I/O (VLIO) Interface OverviewVariable Latency I/O read accesse

6-56 Intel® PXA255 Processor Developer’s Manual Memory Controller6.7.6.1 Variable Latency I/O Timing Diagrams and ParametersFigure 6-21 shows the tim

Intel® PXA255 Processor Developer’s Manual 6-57 Memory ControllerIn Figure 6-21 and Figure 6-22, some of the parameters are defined as follows:• tAS =

xxiv Intel® PXA255 Processor Developer’s Manual Contents

6-58 Intel® PXA255 Processor Developer’s Manual Memory ControllerNote: RDY_sync is an internal signal shown here for clarity. This signal represents

Intel® PXA255 Processor Developer’s Manual 6-59 Memory ControllerIn Figure 6-23 some of the parameters are defined as follows:• tAS = Address setup to

6-60 Intel® PXA255 Processor Developer’s Manual Memory Controller6.8 16-Bit PC Card/Compact Flash InterfaceThe following sections provide information

Intel® PXA255 Processor Developer’s Manual 6-61 Memory ControllerThese are read/write registers. Ignore reads from reserved bits. Write zeros to reser

6-62 Intel® PXA255 Processor Developer’s Manual Memory ControllerTable 6-29. Card Interface Command Assertion Code TableMCMEMx_ASSTMCATTx_ASSTMCIOx_A

Intel® PXA255 Processor Developer’s Manual 6-63 Memory Controller6.8.2 Expansion Memory Configuration Register (MECR)To eliminate external hardware, t

6-64 Intel® PXA255 Processor Developer’s Manual Memory Controller6.8.3 16-Bit PC Card OverviewThe PXA255 processor 16-bit PC Card interface provides

Intel® PXA255 Processor Developer’s Manual 6-65 Memory ControllerWhen writes goes to a card sockets and a byte has been masked via an internal byte en

6-66 Intel® PXA255 Processor Developer’s Manual Memory Controller 6.8.4 External Logic for 16-Bit PC Card ImplementationThe PXA255 processor requires

Intel® PXA255 Processor Developer’s Manual 6-67 Memory ControllerFigure 6-28 shows the glue logic need for a 2-socket system. RDY/nBSY signals are rou

Intel® PXA255 Processor Developer’s Manual 1-1Introduction 1This document applies to the Intel® PXA255 Processor (PXA255 processor). It is an applicat

6-68 Intel® PXA255 Processor Developer’s Manual Memory ControllerFigure 6-28. Expansion Card External Logic for a Two-Socket ConfigurationD(15:0)GPIO

Intel® PXA255 Processor Developer’s Manual 6-69 Memory Controller6.8.5 Expansion Card Interface Timing Diagrams and ParametersFigure 6-29 shows a 16-b

6-70 Intel® PXA255 Processor Developer’s Manual Memory ControllerThe interface waits the smallest possible amount of time (x_ASST_WAIT) before it che

Intel® PXA255 Processor Developer’s Manual 6-71 Memory ControllerFigure 6-31. Alternate Bus Master ModeFigure 6-32. Variable Latency IOProcessorEXTERN

6-72 Intel® PXA255 Processor Developer’s Manual Memory Controller6.9.1 Alternate Bus Master ModeThe processor supports the presence of an alternate m

Intel® PXA255 Processor Developer’s Manual 6-73 Memory Controller7. The Memory Controller performs an SDRAM refresh if SDRAM clocks and clock enable a

6-74 Intel® PXA255 Processor Developer’s Manual Memory Controlleris deasserted or, as part of the sleep entry routine, the alternate master can be di

Intel® PXA255 Processor Developer’s Manual 6-75 Memory ControllerTable 6-40. BOOT_DEF Bitmap0x4800_0044 BOOT_DEF Memory ControllerBit31 30 29 28 27 26

6-76 Intel® PXA255 Processor Developer’s Manual Memory Controller6.10.2.2 Boot-Time ConfigurationsThe boot time configurations are shown in Figure 6-

Intel® PXA255 Processor Developer’s Manual 6-77 Memory ControllerFigure 6-34. SMROM Boot Time Configurations and Register DefaultsBOOT_SEL[2:0] = 100S

1-2 Intel® PXA255 Processor Developer’s Manual Introduction• DMA Controller• LCD Controller• AC97• I2S• MultiMediaCard• FIR Communication• Synchronou

6-78 Intel® PXA255 Processor Developer’s Manual Memory Controller6.10.3 Memory Interface Reset and InitializationOn reset, the SDRAM Interface is dis

Intel® PXA255 Processor Developer’s Manual 6-79 Memory ControllerIn sleep mode, the memory pins and controller are in the same state as they are after

6-80 Intel® PXA255 Processor Developer’s Manual Memory Controllerbeing configured, the SDRAM banks must be disabled and MDREFR:APD must be deasserted

Intel® PXA255 Processor Developer’s Manual 6-81 Memory Controller11. Optionally, in systems that contain SDRAM or Synchronous Static memory, enable au

6-82 Intel® PXA255 Processor Developer’s Manual Memory Controller0x4800_003C MCIO1 Card interface I/O Space Socket 1 Timing Configuration0x4800_0040

Intel® PXA255 Processor Developer’s Manual 7-1LCD Controller 7The LCD controller provides an interface from the PXA255 processor to a passive (DSTN) o

7-2 Intel® PXA255 Processor Developer’s Manual LCD ControllerIn active color display mode, the LCD controller can drive TFT displays. When using 1-,

Intel® PXA255 Processor Developer’s Manual 7-3 LCD ControllerFigure 7-1 illustrates a simplified, top-level block diagram for the processor LCD Contro

7-4 Intel® PXA255 Processor Developer’s Manual LCD Controller7.1.2 Pin DescriptionsWhen the LCD controller is enabled, all of the LCD pins are output

Intel® PXA255 Processor Developer’s Manual 7-5 LCD ControllerIf the LCD controller is being re-enabled, there has not been a reset since the last prog

Intel® PXA255 Processor Developer’s Manual 1-3 Introduction1.2.4 DMA Controller (DMAC)The DMAC provides sixteen prioritized channels to service transf

7-6 Intel® PXA255 Processor Developer’s Manual LCD Controller1, 2, 4, or 8-bits, the FIFO entries are unpacked and used to index the palette RAM to r

Intel® PXA255 Processor Developer’s Manual 7-7 LCD ControllerEither of two matrices may be used for each color, chosen by bits 0, 1, and 14 of the TME

7-8 Intel® PXA255 Processor Developer’s Manual LCD Controller7.3.4 Output FIFOsThe LCD controller has two output FIFOs to queue pixel data before it

Intel® PXA255 Processor Developer’s Manual 7-9 LCD Controller7.3.5.1 Passive Display TimingIn passive display mode (LCCR0[PAS] = 0), L_PCLK toggles on

7-10 Intel® PXA255 Processor Developer’s Manual LCD Controllerunpacked into individual pixel encodings of 1, 2, 4, 8, or 16 bits each. After the valu

Intel® PXA255 Processor Developer’s Manual 7-11 LCD Controller7.4.2 External Frame BufferThe external frame buffer is an off-chip memory area used to

7-12 Intel® PXA255 Processor Developer’s Manual LCD ControllerFigure 7-7. 2 Bits Per Pixel Data Memory OrganizationFigure 7-8. 4 Bits Per Pixel Data

Intel® PXA255 Processor Developer’s Manual 7-13 LCD ControllerFigure 7-10. 16 Bits Per Pixel Data Memory Organization - Passive Mode)Note: For passive

7-14 Intel® PXA255 Processor Developer’s Manual LCD ControllerUse the following equation to calculate the total size of the frame buffer (in bytes).

Intel® PXA255 Processor Developer’s Manual 7-15 LCD ControllerFigure 7-12. Passive Mode Start-of-Frame TimingFigure 7-13. Passive Mode End-of-Frame Ti

1-4 Intel® PXA255 Processor Developer’s Manual Introduction1.2.10 Synchronous Serial Protocol Controller (SSPC)The SSP Port provides a full-duplex sy

7-16 Intel® PXA255 Processor Developer’s Manual LCD ControllerFigure 7-14. Passive Mode Pixel Clock and Data Pin TimingFigure 7-15. Active Mode Timin

Intel® PXA255 Processor Developer’s Manual 7-17 LCD Controller7.6 Register DescriptionsThe LCD controller contains four control registers, ten DMA reg

7-18 Intel® PXA255 Processor Developer’s Manual LCD ControllerThe DMA descriptor addresses are initially programmed by software. After that, the othe

Intel® PXA255 Processor Developer’s Manual 7-19 LCD Controllervalue that causes the FIFO to wait from 0 to 255 clock cycles after the completion of on

7-20 Intel® PXA255 Processor Developer’s Manual LCD ControllerThe LCD pin timing changes when active mode is selected. Timing of each pin is describe

Intel® PXA255 Processor Developer’s Manual 7-21 LCD Controllerstatus register (LCSR) is set, an interrupt request is made to the interrupt controller.

7-22 Intel® PXA255 Processor Developer’s Manual LCD Controller† Double-pixel data mode (DPD) = 1.Color Dual PassiveTop L_DD[7:0]Bottom L_DD[15:8]Colo

Intel® PXA255 Processor Developer’s Manual 7-23 LCD ControllerColor/Monochrome Select (CMS) — selects whether the LCD controller operates in color or

7-24 Intel® PXA255 Processor Developer’s Manual LCD Controller7.6.2 LCD Controller Control Register 1 (LCCR1)LCCR1, shown in Table 7-4, contains four

Intel® PXA255 Processor Developer’s Manual 7-25 LCD ControllerBeginning-of-Line Pixel Clock Wait Count (BLW) — used to specify the number of dummy pix

Intel® PXA255 Processor Developer’s Manual 1-5 Introduction1.2.13.4 Hardware UART (HWUART)The PXA255 processor has a UART with hardware flow control.

7-26 Intel® PXA255 Processor Developer’s Manual LCD Controller7.6.3 LCD Controller Control Register 2 (LCCR2)LCCR2, shown in Table 7-5, contains four

Intel® PXA255 Processor Developer’s Manual 7-27 LCD ControllerIn passive mode, EFW must be set to zero so that no EOF wait states are generated. Use V

7-28 Intel® PXA255 Processor Developer’s Manual LCD ControllerThis is a read/write register. Ignore reads from reserved bits. Write zeros to reserved

Intel® PXA255 Processor Developer’s Manual 7-29 LCD Controller0b011 = 8-bit pixels0b100 = 16-bit pixels0b101–0b111 = reserved Output Enable Polarity (

7-30 Intel® PXA255 Processor Developer’s Manual LCD ControllerIn active display mode (LCCR0[PAS] = 1), L_BIAS is the output enable signal. However, s

Intel® PXA255 Processor Developer’s Manual 7-31 LCD ControllerwhereLCLK = LCD/Memory ClockPCD = LCCR3[7:0]This is a read/write register. Ignore reads

7-32 Intel® PXA255 Processor Developer’s Manual LCD Controller7.6.5 LCD Controller DMAThe LCD controller has two fully independent DMA channels used

Intel® PXA255 Processor Developer’s Manual 7-33 LCD Controllerword[1] contains the value for FSADRxword[2] contains the value for FIDRxword[3] contain

7-34 Intel® PXA255 Processor Developer’s Manual LCD ControllerThese are read-only registers. Ignore reads from reserved bits.7.6.5.4 LCD DMA Frame ID

Intel® PXA255 Processor Developer’s Manual 7-35 LCD Controller7.6.5.5 LCD DMA Command Registers (LDCMDx)LDCMDx, shown in Table 7-10, correspond to DMA

Intel® PXA255 Processor Developer’s Manual iii ContentsContents1 Introduction...

1-6 Intel® PXA255 Processor Developer’s Manual Introduction

7-36 Intel® PXA255 Processor Developer’s Manual LCD ControllerTable 7-10. LDCMDx Bit Definitions Physical Addresschannel 0: 0x4400_020Cchannel 1: 0x4

Intel® PXA255 Processor Developer’s Manual 7-37 LCD Controller7.6.6 LCD DMA Frame Branch Registers (FBRx)FBRx, one for each DMA channel, shown in Tabl

7-38 Intel® PXA255 Processor Developer’s Manual LCD Controller7.6.7 LCD Controller Status Register (LCSR)LCSR, shown in Table 7-12, contains bits tha

Intel® PXA255 Processor Developer’s Manual 7-39 LCD Controllerpanels. When OU is set, an interrupt request is made to the interrupt controller if it i

7-40 Intel® PXA255 Processor Developer’s Manual LCD ControllerTable 7-12. LCSR Bit Definitions (Sheet 1 of 2)Physical Address0x4400_0038LCD Controlle

Intel® PXA255 Processor Developer’s Manual 7-41 LCD Controller7.6.8 LCD Controller Interrupt ID Register (LIIDR)LIIDR, shown in Table 7-13, contains a

7-42 Intel® PXA255 Processor Developer’s Manual LCD Controller7.6.9 TMED RGB Seed Register (TRGBR)TRGBR, shown in Table 7-14 contains the three (red,

Intel® PXA255 Processor Developer’s Manual 7-43 LCD Controller7.6.10 TMED Control Register (TCR)TCR, shown in Table 7-15, selects various options avai

7-44 Intel® PXA255 Processor Developer’s Manual LCD Controller7.7 LCD Controller Register SummaryTable 7-16 shows the registers associated with the L

Intel® PXA255 Processor Developer’s Manual 7-45 LCD Controller0x4400_0024 FBR1 DMA channel 1 frame branch register0x4400_0038 LCSR LCD controller stat

Intel® PXA255 Processor Developer’s Manual 2-1System Architecture 22.1 OverviewThe PXA255 processor is an integrated system-on-a-chip microprocessor f

7-46 Intel® PXA255 Processor Developer’s Manual LCD Controller

Intel® PXA255 Processor Developer’s Manual 8-1Synchronous Serial Port Controller 8This chapter describes the Synchronous Serial Port Controller’s (SSP

8-2 Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port ControllerSSPEXTCLK is an external clock (input through GPIO27) that replaces

Intel® PXA255 Processor Developer’s Manual 8-3 Synchronous Serial Port Controller• SSPRXD–Receive signal for inbound data, from peripheral to system.A

8-4 Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port Controller.8.4.1.2 SPI Format DetailsThe SPI format has four sub-modes. The su

Intel® PXA255 Processor Developer’s Manual 8-5 Synchronous Serial Port ControllerFigure 8-2 shows one of the four configurations for the Motorola SPI

8-6 Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port ControllerFigure 8-3 shows the National Microwire frame format with 8-bit comm

Intel® PXA255 Processor Developer’s Manual 8-7 Synchronous Serial Port Controller8.5 FIFO Operation and Data TransfersTransmit and receive serial data

8-8 Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port Controller8.7 SSP Serial Port RegistersThe SSPC has five registers: two contro

Intel® PXA255 Processor Developer’s Manual 8-9 Synchronous Serial Port Controller8.7.1.1 Data Size Select (DSS)The 4-bit data size select (DSS) field

2-2 Intel® PXA255 Processor Developer’s Manual System Architecture2.2 Intel XScale® Microarchitecture Implementation OptionsThe processor incorporate

8-10 Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port Controllertransmit FIFO. The transmit logic in the SSPC left-justifies the da

Intel® PXA255 Processor Developer’s Manual 8-11 Synchronous Serial Port Controller8.7.1.5 Serial Clock Rate (SCR)The 8-bit serial clock rate (SCR) bit

8-12 Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port Controller8.7.2.1 Receive FIFO Interrupt Enable (RIE)The Receive FIFO Interru

Intel® PXA255 Processor Developer’s Manual 8-13 Synchronous Serial Port ControllerNote: Loop back mode cannot be used with Microwire frame format.8.7.

8-14 Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port Controller8.7.2.6 Microwire Transmit Data Size (MWDS)The Microwire Transmit D

Intel® PXA255 Processor Developer’s Manual 8-15 Synchronous Serial Port ControllerThis is a read/write register. Ignore reads from reserved bits. Writ

8-16 Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port Controller8.7.4 SSP Status Register (SSSR)The SSP Status Register (SSSR) is s

Intel® PXA255 Processor Developer’s Manual 8-17 Synchronous Serial Port Controller8.7.4.1 Transmit FIFO Not Full Flag (TNF)This non-interruptible bit

8-18 Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port Controller8.7.4.2 Receive FIFO Not Empty Flag (RNE)This non-interruptible bit

Intel® PXA255 Processor Developer’s Manual 8-19 Synchronous Serial Port Controller8.7.4.8 Receive FIFO Level (RFL)This bit indicates the one less than

Intel® PXA255 Processor Developer’s Manual 2-3 System Architecture2.2.2 Coprocessor 14 Registers 0-3 - Performance MonitoringThe processor does not de

8-20 Intel® PXA255 Processor Developer’s Manual Synchronous Serial Port Controller

Intel® PXA255 Processor Developer’s Manual 9-1I2C Bus Interface Unit 9This chapter describes the Inter-Integrated Circuit (I2C) bus interface unit, in

9-2 Intel® PXA255 Processor Developer’s Manual I2C Bus Interface UnitFor example, when the processor I2C unit acts as a master on the bus, it address

Intel® PXA255 Processor Developer’s Manual 9-3 I2C Bus Interface Unit9.3.1 Operational BlocksThe I2C unit is connected to the peripheral bus. The proc

9-4 Intel® PXA255 Processor Developer’s Manual I2C Bus Interface UnitWhen the I2C unit receives an address that matches the 7-bit address found in th

Intel® PXA255 Processor Developer’s Manual 9-5 I2C Bus Interface UnitFigure 9-2 shows the relationship between the SDA and SCL lines for START and STO

9-6 Intel® PXA255 Processor Developer’s Manual I2C Bus Interface UnitFigure 9-3. START and STOP ConditionsData byteACK/NAKACK/NAKR/nWSTART Target Sla

Intel® PXA255 Processor Developer’s Manual 9-7 I2C Bus Interface Unit9.4 I2C Bus OperationThe I2C unit transfers data in 1-byte increments and always

9-8 Intel® PXA255 Processor Developer’s Manual I2C Bus Interface Unit9.4.2.1 Addressing a Slave DeviceAs a master device, the I2C unit must compose a

Intel® PXA255 Processor Developer’s Manual 9-9 I2C Bus Interface UnitIn master-transmit mode, if the target slave-receiver device cannot generate the

2-4 Intel® PXA255 Processor Developer’s Manual System Architecture2.2.5 Coprocessor 15 Register 1 - P-BitBit 1 of this register is defined as the Pag

9-10 Intel® PXA255 Processor Developer’s Manual I2C Bus Interface UnitArbitration can take a long time. If the address bit and the R/nW are the same,

Intel® PXA255 Processor Developer’s Manual 9-11 I2C Bus Interface UnitIf the I2C unit loses arbitration as the address bits are transferred and it is

9-12 Intel® PXA255 Processor Developer’s Manual I2C Bus Interface Unit9.4.6 Master OperationsWhen software initiates a read or write on the I2C bus,

Intel® PXA255 Processor Developer’s Manual 9-13 I2C Bus Interface UnitWhen the CPU needs to read data, the I2C unit transitions from slave-receive mod

9-14 Intel® PXA255 Processor Developer’s Manual I2C Bus Interface Unit. \9.4.7 Slave OperationsTable 9-6 describes how the I2C unit operates as a sla

Intel® PXA255 Processor Developer’s Manual 9-15 I2C Bus Interface UnitFigure 9-11 through Figure 9-13 are examples of I2C transactions and show the re

9-16 Intel® PXA255 Processor Developer’s Manual I2C Bus Interface Unit9.4.8 General Call AddressA general call address is a transaction with a slave

Intel® PXA255 Processor Developer’s Manual 9-17 I2C Bus Interface UnitThe I2C unit supports sending and receiving general call address transfers on th

9-18 Intel® PXA255 Processor Developer’s Manual I2C Bus Interface Unit9.5 Slave Mode Programming Examples9.5.1 Initialize Unit1. Set the slave addres

Intel® PXA255 Processor Developer’s Manual 9-19 I2C Bus Interface Unit5. When an IDBR Receive Full interrupt occurs. Read ISR: IDBR Receive Full (1),

Intel® PXA255 Processor Developer’s Manual 2-5 System Architecture2.3 I/O OrderingThe processor uses queues that accept memory requests from the three

9-20 Intel® PXA255 Processor Developer’s Manual I2C Bus Interface Unit9.6.3 Read 1 Byte as a Master1. Load target slave address and R/nW bit in the I

Intel® PXA255 Processor Developer’s Manual 9-21 I2C Bus Interface Unit16. Write a 1 to the ISR[IRF] bit to clear the interrupt.17. Read IDBR data.18.

9-22 Intel® PXA255 Processor Developer’s Manual I2C Bus Interface UnitWhen the ICR[UR] bit is set, the I2C unit resets but the associated I2C MMRs re

Intel® PXA255 Processor Developer’s Manual 9-23 I2C Bus Interface Uniton the acknowledge pulse in receiver mode. After the processor reads the IDBR, t

9-24 Intel® PXA255 Processor Developer’s Manual I2C Bus Interface Unit10 BEIEBus Error Interrupt Enable:0 = Disable interrupt.1 = Enables the I2C uni

Intel® PXA255 Processor Developer’s Manual 9-25 I2C Bus Interface Unit9.9.4 I2C Status Register (ISR)The ISR, shown in Table 9-11, signals I2C interru

9-26 Intel® PXA255 Processor Developer’s Manual I2C Bus Interface UnitTable 9-11. ISR Bit Definitions (Sheet 1 of 2)Physical Address4030_1698I2C Sta

Intel® PXA255 Processor Developer’s Manual 9-27 I2C Bus Interface Unit9.9.5 I2C Slave Address Register (ISAR)The ISAR, shown in Table 9-12, defines th

9-28 Intel® PXA255 Processor Developer’s Manual I2C Bus Interface Unit

Intel® PXA255 Processor Developer’s Manual 10-1UARTs 10This chapter describes the universal asynchronous receiver/transmitter (UART) serial ports. The

2-6 Intel® PXA255 Processor Developer’s Manual System ArchitectureEach interrupt goes through the Interrupt Controller Mask Register and then the Int

10-2 Intel® PXA255 Processor Developer’s Manual UARTs10.2 OverviewEach serial port contains a UART and a slow infrared transmit encoder and receive d

Intel® PXA255 Processor Developer’s Manual 10-3 UARTs10.3 Signal DescriptionsTable 10-1 lists and describes each external signal that is connected to

10-4 Intel® PXA255 Processor Developer’s Manual UARTs10.4 UART Operational DescriptionThe format of a UART data frame is shown in Figure 10-1.Receive

Intel® PXA255 Processor Developer’s Manual 10-5 UARTsor if odd parity is enabled and the data byte has an even number of ones. The data frame ends wit

10-6 Intel® PXA255 Processor Developer’s Manual UARTs.10.4.2.1 Receive Buffer Register (RBR)In non-FIFO mode, the RBR, shown in Table 10-3 , holds th

Intel® PXA255 Processor Developer’s Manual 10-7 UARTs10.4.2.2 Transmit Holding Register (THR)In non-FIFO mode, the THR, shown in Table 10-4, holds the

10-8 Intel® PXA255 Processor Developer’s Manual UARTs10.4.2.4 Interrupt Enable Register (IER)The IER, shown in Table 10-7, enables the five types of

Intel® PXA255 Processor Developer’s Manual 10-9 UARTsBit 7 of the IER is used to enable DMA requests. The IER also contains the unit enable and NRZ co

10-10 Intel® PXA255 Processor Developer’s Manual UARTsIn FIFO mode, the “Received Data is available” interrupt (Priority Level 2) takes priority over

Intel® PXA255 Processor Developer’s Manual 10-11 UARTs3TOD(IID3)Character Timeout Indication Detected:0 – No Character Timeout Indication interrupt is

Intel® PXA255 Processor Developer’s Manual 2-7 System Architecture2.7 Internal RegistersAll internal registers are mapped in physical memory space on

10-12 Intel® PXA255 Processor Developer’s Manual UARTs10.4.2.6 FIFO Control Register (FCR)The FCR, shown in Table 10-11, is a write-only register tha

Intel® PXA255 Processor Developer’s Manual 10-13 UARTs10.4.2.7 Line Control Register (LCR)The LCR, shown in Table 10-12, specifies the format for the

10-14 Intel® PXA255 Processor Developer’s Manual UARTsTable 10-12. LCR Bit Definitions Base+0x0C Line Control Register UARTBit31 30 29 28 27 26 25 24

Intel® PXA255 Processor Developer’s Manual 10-15 UARTs10.4.2.8 Line Status Register (LSR)The LSR, shown in Table 10-13, provides data transfer status

10-16 Intel® PXA255 Processor Developer’s Manual UARTs5TDRQTransmit Data Request: Indicates that the UART is ready to accept a new character for tran

Intel® PXA255 Processor Developer’s Manual 10-17 UARTs2PEParity Error: Indicates that the received data character does not have the correct even or od

10-18 Intel® PXA255 Processor Developer’s Manual UARTs10.4.2.9 Modem Control Register (MCR)The MCR, shown in Table 10-14, uses the modem control pins

Intel® PXA255 Processor Developer’s Manual 10-19 UARTs10.4.2.10 Modem Status Register (MSR)The MSR, shown in Table 10-15, provides the current state o

10-20 Intel® PXA255 Processor Developer’s Manual UARTsTable 10-15. MSR Bit Definitions Base+0x18 Modem Status Register UARTBit31 30 29 28 27 26 25 24

Intel® PXA255 Processor Developer’s Manual 10-21 UARTs10.4.2.11 Scratchpad Register (SPR)The SPR, shown in Table 10-16, has no effect on the UART. It

2-8 Intel® PXA255 Processor Developer’s Manual System Architecture2.9 Power on Reset and Boot OperationBefore the device that uses the processor is p

10-22 Intel® PXA255 Processor Developer’s Manual UARTsAfter the processor reads one character from the receive FIFO or a new start bit is received, t

Intel® PXA255 Processor Developer’s Manual 10-23 UARTsNote: Ensure that the DMAC has finished previous receive DMA requests before the error interrupt

10-24 Intel® PXA255 Processor Developer’s Manual UARTs10.4.6.2 OperationThe SIR modulation technique works with 5-, 6-, 7-, or 8-bit characters with

Intel® PXA255 Processor Developer’s Manual 10-25 UARTsThe top line in Figure 10-3 shows an asynchronous transmission as it is sent from the UART. The

10-26 Intel® PXA255 Processor Developer’s Manual UARTsthe Transmit FIFO will not be held. Only add data to the Transmit FIFO while not receiving. To

Intel® PXA255 Processor Developer’s Manual 10-27 UARTs0x4020_001C X BTSPR Scratch Pad Register0x4020_0020 X BTISR Infrared Selection register (read/wr

10-28 Intel® PXA255 Processor Developer’s Manual UARTs10.5.1 UART Register DifferencesThe default descriptions for BTMCR, BTMSR and STMCR are modifie

Intel® PXA255 Processor Developer’s Manual 11-1Fast Infrared Communication Port 11The Fast Infrared Communications Port (FICP) for the PXA255 processo

11-2 Intel® PXA255 Processor Developer’s Manual Fast Infrared Communication Port11.2.1 4PPM ModulationFour-position pulse modulation (4PPM) is used t

Intel® PXA255 Processor Developer’s Manual 11-3 Fast Infrared Communication Port11.2.2 Frame FormatThe frame format used with 4-Mbps transmission is s

Intel® PXA255 Processor Developer’s Manual 2-9 System ArchitectureTable 2-6 describes the PXA255 processor pins.IA Analog InputOA Analog outputIAOA An

11-4 Intel® PXA255 Processor Developer’s Manual Fast Infrared Communication Port11.2.6 CRC FieldThe FICP uses a 32-bit Cyclic Redundancy Check (CRC)

Intel® PXA255 Processor Developer’s Manual 11-5 Fast Infrared Communication PortAfter 16 preambles are transmitted, the start flag is received. The st

11-6 Intel® PXA255 Processor Developer’s Manual Fast Infrared Communication PortA minimum of 16 preambles are transmitted for each frame. If data is

Intel® PXA255 Processor Developer’s Manual 11-7 Fast Infrared Communication PortWhen the transmit FIFO has 32 or more empty bytes, the transmit DMA re

11-8 Intel® PXA255 Processor Developer’s Manual Fast Infrared Communication Port11.3.1 FICP Control Register 0 (ICCR0)The ICCR0, shown in Table 11-2,

Intel® PXA255 Processor Developer’s Manual 11-9 Fast Infrared Communication Port3TXETransmit enable. 0 = FICP transmit logic disabled.1 = FICP transmi

11-10 Intel® PXA255 Processor Developer’s Manual Fast Infrared Communication Port11.3.2 FICP Control Register 1 (ICCR1)The ICCR1, shown in Table 11-3

Intel® PXA255 Processor Developer’s Manual 11-11 Fast Infrared Communication Port11.3.3 FICP Control Register 2 (ICCR2)The ICCR2, shown in Table 11-4,

11-12 Intel® PXA255 Processor Developer’s Manual Fast Infrared Communication Port11.3.4 FICP Data Register (ICDR)The ICDR, shown in Table 11-5, is a

Intel® PXA255 Processor Developer’s Manual 11-13 Fast Infrared Communication Port11.3.5 FICP Status Register 0 (ICSR0)The ICSR0, shown in Table 11-6,

iv Intel® PXA255 Processor Developer’s Manual Contents3.3.1 32.768 kHz Oscillator...

2-10 Intel® PXA255 Processor Developer’s Manual System ArchitectureSDCLK[1] OCZ SDRAM Clocks (output) Connect SDCLK[1] and SDCLK[2] to the clock pins

11-14 Intel® PXA255 Processor Developer’s Manual Fast Infrared Communication Port2RABReceiver abort.0 = No abort has been detected for the incoming f

Intel® PXA255 Processor Developer’s Manual 11-15 Fast Infrared Communication Port11.3.6 FICP Status Register 1 (ICSR1)ICSR1, shown in Table 11-7, cont

11-16 Intel® PXA255 Processor Developer’s Manual Fast Infrared Communication Port11.4 FICP Register SummaryTable 11-8 shows the registers associated

Intel® PXA255 Processor Developer’s Manual 12-1USB Device Controller 12This section describes the Universal Serial Bus (USB) protocol and its implemen

12-2 Intel® PXA255 Processor Developer’s Manual USB Device Controller12-Mbps device and provides the correct polarity for data transmission. The seri

Intel® PXA255 Processor Developer’s Manual 12-3 USB Device Controller12.3.1 Signalling LevelsUSB uses differential signalling to encode data and to in

12-4 Intel® PXA255 Processor Developer’s Manual USB Device Controllerincoming data, which produces the clock. To ensure the receiver is periodically

Intel® PXA255 Processor Developer’s Manual 12-5 USB Device ControllerThe Frame Number is an 11-bit field incremented by the host each time a frame is

12-6 Intel® PXA255 Processor Developer’s Manual USB Device Controller12.3.4.3 Data Packet TypeData packets follow Token packets and are used to trans

Intel® PXA255 Processor Developer’s Manual 12-7 USB Device Controller12.3.5.2 Isochronous Transaction TypeIsochronous transactions ensure constant rat

Intel® PXA255 Processor Developer’s Manual 2-11 System ArchitecturenPIOW/GPIO[51]ICOCZPCMCIA I/O write. (output) Performs write transactions to PCMCIA

12-8 Intel® PXA255 Processor Developer’s Manual USB Device ControllerTo assemble control transfers, the host sends a control transaction to tell the

Intel® PXA255 Processor Developer’s Manual 12-9 USB Device ControllerThe UDC decodes most standard device commands with no intervention required by th

12-10 Intel® PXA255 Processor Developer’s Manual USB Device ControllerThe direction of the endpoints is fixed. Physically, the UDC only supports inte

Intel® PXA255 Processor Developer’s Manual 12-11 USB Device Controller12.4.1.1 When GPIOn and GPIOx are Different PinsThe GPIOn and GPIOx pins can be

12-12 Intel® PXA255 Processor Developer’s Manual USB Device Controller12.4.2 Bus-Powered DevicesThe processor does not support bus-powered devices be

Intel® PXA255 Processor Developer’s Manual 12-13 USB Device Controller14. When the host executes the STATUS OUT stage (zero-length OUT), the UDC sets

12-14 Intel® PXA255 Processor Developer’s Manual USB Device Controller16. Software clears the UDC interrupt bit and returns from the interrupt servic

Intel® PXA255 Processor Developer’s Manual 12-15 USB Device Controllerthe wrong amount of data was sent, software cleans up any buffer pointers and di

12-16 Intel® PXA255 Processor Developer’s Manual USB Device Controller1. During the SETUP VENDOR command, software enables the DMA engine and masks t

Intel® PXA255 Processor Developer’s Manual 12-17 USB Device Controller2. The host PC sends a BULK-OUT.3. The DMA engine reads data from the EP2 data F

2-12 Intel® PXA255 Processor Developer’s Manual System ArchitectureL_DD[13]/GPIO[71]ICOCZLCD display data. (output) Transfers pixel information from

12-18 Intel® PXA255 Processor Developer’s Manual USB Device Controller1. During the SETUP VENDOR command, software enables the DMA engine and masks t

Intel® PXA255 Processor Developer’s Manual 12-19 USB Device ControllerWhen software receives a SETUP VENDOR command to set up an EP4 ISOCHRONOUS OUT t

12-20 Intel® PXA255 Processor Developer’s Manual USB Device Controller6. Return from interrupt.7. Steps 2 through 6 repeat until all the data has bee

Intel® PXA255 Processor Developer’s Manual 12-21 USB Device Controllerb. If UDCCR[UDA] is a 1, there is currently no USB reset on the bus and software

12-22 Intel® PXA255 Processor Developer’s Manual USB Device Controlleraddress for the 16 x 8 data FIFO that can be used to transmit and receive data.

Intel® PXA255 Processor Developer’s Manual 12-23 USB Device Controller12.6.1.2 UDC Active (UDA)This read-only bit can be read to determine if the UDC

12-24 Intel® PXA255 Processor Developer’s Manual USB Device Controller12.6.2 UDC Control Function Register (UDCCFR)The UDC Control Function register

Intel® PXA255 Processor Developer’s Manual 12-25 USB Device ControllerSET_CONFIGURAION and SET_INTERFACE command with a NAK until AREN is set to 1. Wh

12-26 Intel® PXA255 Processor Developer’s Manual USB Device ControllerUDCCS0[FTF] bit has been set, or a control OUT is received. When this bit is cl

Intel® PXA255 Processor Developer’s Manual 12-27 USB Device Controller12.6.3.8 Setup Active (SA)The Setup Active bit indicates that the current packet

Intel® PXA255 Processor Developer’s Manual 2-13 System ArchitectureBTCTS/GPIO[44]ICOCZ Bluetooth UART Clear-to-Send. (input)Pulled High - Note[1]Note

12-28 Intel® PXA255 Processor Developer’s Manual USB Device Controller12.6.4.2 Transmit Packet Complete (TPC)The transmit packet complete bit is set

Intel® PXA255 Processor Developer’s Manual 12-29 USB Device Controller12.6.4.8 Transmit Short Packet (TSP)The software uses the transmit short packet

12-30 Intel® PXA255 Processor Developer’s Manual USB Device Controller12.6.5.1 Receive FIFO Service (RFS)The receive FIFO service bit is set if the r

Intel® PXA255 Processor Developer’s Manual 12-31 USB Device Controller12.6.5.7 Receive FIFO Not Empty (RNE)The receive FIFO not empty bit indicates th

12-32 Intel® PXA255 Processor Developer’s Manual USB Device Controller12.6.6.1 Transmit FIFO Service (TFS)The transmit FIFO service bit is be set if

Intel® PXA255 Processor Developer’s Manual 12-33 USB Device Controller12.6.7.1 Receive FIFO Service (RFS)The receive FIFO service bit is set if the re

12-34 Intel® PXA255 Processor Developer’s Manual USB Device Controller12.6.7.4 DMA Enable (DME)The DMA enable is used by the UDC to control the timin

Intel® PXA255 Processor Developer’s Manual 12-35 USB Device Controller12.6.8.1 Transmit FIFO Service (TFS)The transmit FIFO service bit is set if the

12-36 Intel® PXA255 Processor Developer’s Manual USB Device Controller12.6.8.4 Transmit Underrun (TUR)The transmit underrun bit is be set if the tran

Intel® PXA255 Processor Developer’s Manual 12-37 USB Device Controller12.6.9.1 Interrupt Mask Endpoint x (IMx), Where x is 0 through 7The UICR0[IMx] b

2-14 Intel® PXA255 Processor Developer’s Manual System ArchitectureMMCCLK/GP[6] ICOCZMMC clock. (output) Clock signal for the MMC Controller.Pulled H

12-38 Intel® PXA255 Processor Developer’s Manual USB Device Controller12.6.10 UDC Interrupt Control Register 1 (UICR1)UICR1, shown in Table 12-21, co

Intel® PXA255 Processor Developer’s Manual 12-39 USB Device Controller12.6.11 UDC Status/Interrupt Register 0 (USIR0)USIR0, shown in Table 12-22, and

12-40 Intel® PXA255 Processor Developer’s Manual USB Device Controller12.6.11.3 Endpoint 2 Interrupt Request (IR2)The interrupt request bit is set if

Intel® PXA255 Processor Developer’s Manual 12-41 USB Device Controller12.6.12 UDC Status/Interrupt Register 1 (USIR1)12.6.12.1 Endpoint 8 Interrupt Re

12-42 Intel® PXA255 Processor Developer’s Manual USB Device Controller12.6.12.4 Endpoint 11 Interrupt Request (IR11)The interrupt request bit is set

Intel® PXA255 Processor Developer’s Manual 12-43 USB Device Controller12.6.13.1 UDC Frame Number MSB (FNMSB)The UFNHR[FNMSB] is the three most signifi

12-44 Intel® PXA255 Processor Developer’s Manual USB Device Controller12.6.13.4 Isochronous Packet Error Endpoint 14 (IPE14)The isochronous packet er

Intel® PXA255 Processor Developer’s Manual 12-45 USB Device Controller12.6.15.1 Endpoint x Byte Count (BC)The byte count is updated after each byte is

12-46 Intel® PXA255 Processor Developer’s Manual USB Device Controller12.6.17 UDC Endpoint x Data Register (UDDR1/6/11)UDDR1/6/11, shown in Table 12-

Intel® PXA255 Processor Developer’s Manual 12-47 USB Device ControllerThese are read-only registers. Ignore reads from reserved bits. 12.6.19 UDC Endp

Intel® PXA255 Processor Developer’s Manual 2-15 System ArchitectureSDATA_OUT/GPIO[30]ICOCZAC97 Audio Port data out. (output) Output from the PXA255 pr

12-48 Intel® PXA255 Processor Developer’s Manual USB Device Controller12.6.21 UDC Endpoint x Data Register (UDDR5/10/15)UDDR5/10/15, shown in Table 1

Intel® PXA255 Processor Developer’s Manual 12-49 USB Device Controller0x4060_0010 UDCCS0 UDC Endpoint 0 Control/Status Register0x4060_0014 UDCCS1 UDC

12-50 Intel® PXA255 Processor Developer’s Manual USB Device Controller0x4060_00C0 UDDR10 UDC Endpoint 10 Data Register0x4060_0B00 UDDR11 UDC Endpoint

Intel® PXA255 Processor Developer’s Manual 13-1AC’97 Controller Unit 1313.1 OverviewThe AC’97 Controller Unit (ACUNIT) of the PXA255 processor support

13-2 Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit13.3 Signal DescriptionThe AC’97 signals form the AC-link, which is a point-to-p

Intel® PXA255 Processor Developer’s Manual 13-3 AC’97 Controller Unit13.4 AC-link Digital Serial Interface ProtocolEach AC’97 CODEC incorporates a fiv

13-4 Intel® PXA255 Processor Developer’s Manual AC’97 Controller UnitThe ACUNIT provides synchronization for all data transaction on the AC-link. A d

Intel® PXA255 Processor Developer’s Manual 13-5 AC’97 Controller UnitA new audio output frame begins with a low-to-high SYNC transition synchronous to

13-6 Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit13.4.1.1 Slot 0: Tag PhaseIn slot 0, the first bit is a global bit (SDATA_OUT sl

Intel® PXA255 Processor Developer’s Manual 13-7 AC’97 Controller UnitOnly one I/O cycle can be pending across the AC-link at any time. The ACUNIT uses

2-16 Intel® PXA255 Processor Developer’s Manual System Architecture48MHz/GP[7] ICOCZ48 MHz clock. (output) Peripheral clock output derived from the P

13-8 Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit13.4.1.5 Slot 4: PCM Playback Right ChannelSlot 4 is the composite digital audio

Intel® PXA255 Processor Developer’s Manual 13-9 AC’97 Controller UnitA new audio input frame begins when SYNC transitions from low to high. The low to

13-10 Intel® PXA255 Processor Developer’s Manual AC’97 Controller UnitCODEC Ready, sent by the CODEC on its data out stream in bit 15 of Slot 0, is n

Intel® PXA255 Processor Developer’s Manual 13-11 AC’97 Controller UnitSLOTREQ bits are independent of the Control Register Index bits.Note: Slot reque

13-12 Intel® PXA255 Processor Developer’s Manual AC’97 Controller UnitThe ACUNIT only supports a 16-bit resolution from the microphone.13.4.2.8 Slots

Intel® PXA255 Processor Developer’s Manual 13-13 AC’97 Controller UnitThe ACUNIT transmits the write to the Powerdown Register (0x26) over the AC-link

13-14 Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit13.5.2.2 Wake Up Triggered by the ACUNITAC-link protocol provides for a cold AC

Intel® PXA255 Processor Developer’s Manual 13-15 AC’97 Controller UnitReceive FIFO entries are read through the PCDR, the MODR, or the Mic-in Data Reg

13-16 Intel® PXA255 Processor Developer’s Manual AC’97 Controller UnitACUNIT does not set the CODEC-ready bit, GCR[PCRDY] for the Primary CODEC or GC

Intel® PXA255 Processor Developer’s Manual 13-17 AC’97 Controller Unit13.6.2 Trailing bytesTrailing bytes in the transmit and receive FIFOs are handle

Intel® PXA255 Processor Developer’s Manual 2-17 System ArchitectureTDO OCZJTAG test data output. (output) Data from the PXA255 processor is returned t

13-18 Intel® PXA255 Processor Developer’s Manual AC’97 Controller UnitAll data transfers across the AC-link are synchronized to SYNC’s rising edge. T

Intel® PXA255 Processor Developer’s Manual 13-19 AC’97 Controller Unit13.8.2 InterruptsThe following status bits interrupt the processor when the inte

13-20 Intel® PXA255 Processor Developer’s Manual AC’97 Controller UnitChannel specific data registers are for FIFO accesses and the PCM, Modem, and M

Intel® PXA255 Processor Developer’s Manual 13-21 AC’97 Controller Unit13.8.3.2 Global Status Register (GSR)This is a read/write register. Ignore reads

13-22 Intel® PXA255 Processor Developer’s Manual AC’97 Controller UnitTable 13-8. GSR Bit Definitions (Sheet 1 of 2)Physical Address4050_001CGSR Regi

Intel® PXA255 Processor Developer’s Manual 13-23 AC’97 Controller Unit13.8.3.3 PCM-Out Control Register (POCR)This is a read/write register. Ignore re

13-24 Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit13.8.3.4 PCM-In Control Register (PICR)This is a read/write register. Ignore re

Intel® PXA255 Processor Developer’s Manual 13-25 AC’97 Controller Unit13.8.3.5 PCM-Out Status Register (POSR)This is a read/write register. Ignore rea

13-26 Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit13.8.3.7 CODEC Access Register (CAR) This is a read/write register. Ignore read

Intel® PXA255 Processor Developer’s Manual 13-27 AC’97 Controller Unit13.8.3.9 Mic-In Control Register (MCCR)This is a read/write register. Ignore rea

2-18 Intel® PXA255 Processor Developer’s Manual System Architecture2.12 Memory MapFigure 2-2 and Figure 2-3 show the full processor memory map.Any un

13-28 Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit13.8.3.11 Mic-In Data Register (MCDR)The Mic-In Data Register is a read-only re

Intel® PXA255 Processor Developer’s Manual 13-29 AC’97 Controller Unit13.8.3.12 Modem-Out Control Register (MOCR)This is a read/write register. Ignore

13-30 Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit13.8.3.14 Modem-Out Status Register (MOSR)This is a read/write register. Ignore

Intel® PXA255 Processor Developer’s Manual 13-31 AC’97 Controller Unit13.8.3.16 Modem Data Register (MODR)This is a read/write register. Ignore reads

13-32 Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit13.8.3.17 Accessing CODEC Registers Each CODEC has up to sixty-four 16-bit regi

Intel® PXA255 Processor Developer’s Manual 13-33 AC’97 Controller UnitTable 13-23. Address Mapping for CODEC Registers (Sheet 1 of 2)7-bit CODEC Addre

13-34 Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit0x44 0x4050_0288 0x4050_0388 0x4050_0488 0x4050_05880x46 0x4050_028C 0x4050_038

Intel® PXA255 Processor Developer’s Manual 13-35 AC’97 Controller Unit13.9 AC’97 Register SummaryAll AC’97 registers are word-addressable (32 bits wid

13-36 Intel® PXA255 Processor Developer’s Manual AC’97 Controller Unit

Intel® PXA255 Processor Developer’s Manual 14-1Inter-Integrated-Circuit Sound (I2S) Controller 14I2S is a protocol for digital stereo audio. The I2S C

Intel® PXA255 Processor Developer’s Manual 2-19 System ArchitectureFigure 2-2. Memory Map (Part One) — From 0x8000_0000 to 0xFFFF FFFFReserved (64 MB)

14-2 Intel® PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound (I2S) Controller14.2 Signal DescriptionsSYSCLK is the clock on which a

Intel® PXA255 Processor Developer’s Manual 14-3 Inter-Integrated-Circuit Sound (I2S) Controller2. Program SYSUNIT’s GPIO Alternate Function Select Reg

14-4 Intel® PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound (I2S) Controller2. Choose between Normal I2S or MSB-Justified modes of

Intel® PXA255 Processor Developer’s Manual 14-5 Inter-Integrated-Circuit Sound (I2S) ControllerAsserting the DREC bit in SACR1 has the following effec

14-6 Intel® PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound (I2S) ControllerThe BITCLK, as shown in Table 14-2, is different for d

Intel® PXA255 Processor Developer’s Manual 14-7 Inter-Integrated-Circuit Sound (I2S) ControllerFigure 14-1 and Figure 14-2 provide timing diagrams tha

14-8 Intel® PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound (I2S) Controller14.6 RegistersThe I2S Controller registers are all 32-

Intel® PXA255 Processor Developer’s Manual 14-9 Inter-Integrated-Circuit Sound (I2S) Controller14.6.1.1 Special purpose FIFO Read/Write functionAs sho

14-10 Intel® PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound (I2S) Controller14.6.1.2 Suggested TFTH and RFTH for DMA servicingThe

Intel® PXA255 Processor Developer’s Manual 14-11 Inter-Integrated-Circuit Sound (I2S) Controller14.6.3 Serial Audio Controller I2S/MSB-Justified Statu

Intel® PXA255 Processor Developer’s Manual v Contents4.2 Interrupt Controller...

2-20 Intel® PXA255 Processor Developer’s Manual System ArchitectureFigure 2-3. Memory Map (Part Two) — From 0x0000_0000 to 0x7FFF FFFF Reserved (64 M

14-12 Intel® PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound (I2S) Controller14.6.4 Serial Audio Clock Divider Register (SADIV)SAD

Intel® PXA255 Processor Developer’s Manual 14-13 Inter-Integrated-Circuit Sound (I2S) ControllerThe reset value, 0x0000001A, defaults to a sampling fr

14-14 Intel® PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound (I2S) Controller14.6.6 Serial Audio Interrupt Mask Register (SAIMR)Wr

Intel® PXA255 Processor Developer’s Manual 14-15 Inter-Integrated-Circuit Sound (I2S) Controller14.7 InterruptsThe following SASR0 status bits, if ena

14-16 Intel® PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound (I2S) ControllerTable 14-12. Register Memory Map Address(paddr(9:0)Re

Intel® PXA255 Processor Developer’s Manual 15-1MultiMediaCard Controller 1515.1 OverviewThe PXA255 processor MultiMediaCard (MMC) controller acts as a

15-2 Intel® PXA255 Processor Developer’s Manual MultiMediaCard ControllerThe MMC bus connects the card stack to the controller. The software and cont

Intel® PXA255 Processor Developer’s Manual 15-3 MultiMediaCard Controllerthe bidirectional MMDAT signal. A typical MMC mode command timing diagram wit

15-4 Intel® PXA255 Processor Developer’s Manual MultiMediaCard ControllerNote: One- and three-byte data transfers are not supported with this control

Intel® PXA255 Processor Developer’s Manual 15-5 MultiMediaCard ControllerThe MMC controller is the interface between the software and the MMC bus. It

Intel® PXA255 Processor Developer’s Manual 2-21 System Architecture2.13 System Architecture Register SummaryTable 2-8. System Architecture Register Ad

15-6 Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller15.2.1 Signal DescriptionThe MMC controller signals are MMCLK, MMCMD, MMDAT,

Intel® PXA255 Processor Developer’s Manual 15-7 MultiMediaCard Controller15.2.4.1 MMC ModeIn MMC mode, the MMCMD and MMDAT signals are bidirectional a

15-8 Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller15.2.4.2 SPI ModeSPI mode is an optional secondary communication protocol. I

Intel® PXA255 Processor Developer’s Manual 15-9 MultiMediaCard Controller15.2.7 Clock ControlBoth the MMC controller and the software can control the

15-10 Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller15.2.8 Data FIFOsThe controller FIFOs for the response tokens, received dat

Intel® PXA255 Processor Developer’s Manual 15-11 MultiMediaCard ControllerIf the DMA is used, it must be programmed to do 1-byte reads of 32-byte burs

15-12 Intel® PXA255 Processor Developer’s Manual MultiMediaCard ControllerWhen the DMA is used, it must be programmed to do 1-byte writes of 32-byte

Intel® PXA255 Processor Developer’s Manual 15-13 MultiMediaCard Controller15.3.1 Basic, No Data, Command and Response SequenceThe MMC controller perfo

15-14 Intel® PXA255 Processor Developer’s Manual MultiMediaCard ControllerAfter completely reading or writing the data FIFOs, the software must wait

Intel® PXA255 Processor Developer’s Manual 15-15 MultiMediaCard Controller15.3.2.2 Block Data ReadIn a single block data read, a block of data is read

2-22 Intel® PXA255 Processor Developer’s Manual System Architecture0x4000_014C DRCMR19 Request to Channel Map Register for STUART receive Request0x40

15-16 Intel® PXA255 Processor Developer’s Manual MultiMediaCard ControllerIn a stream data write, the following parameters must be specified:• The da

Intel® PXA255 Processor Developer’s Manual 15-17 MultiMediaCard Controller15.3.4 SPI FunctionalityThe MMC controller can address up to two cards in SP

15-18 Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller3. MMC_SPI[SPI_CS_ADDRESS] must be set to specify the card that the softwar

Intel® PXA255 Processor Developer’s Manual 15-19 MultiMediaCard Controller• Update the MMC_CMDAT register as:— Write 0x01 to MMC_CMDAT[RESPONSE_FORMAT

15-20 Intel® PXA255 Processor Developer’s Manual MultiMediaCard ControllerThese registers must be set before the clock is started:• Update these MMC_

Intel® PXA255 Processor Developer’s Manual 15-21 MultiMediaCard Controller15.4.10 Stream WriteIn a stream write command, the software must stop the cl

15-22 Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller• Set MMC_BLKLEN register to the number of bytes per block.• Update the MMC

Intel® PXA255 Processor Developer’s Manual 15-23 MultiMediaCard Controller15.5.2 MMC_Status Register (MMC_STAT)MMC_STAT, shown in Table 15-6, is the s

15-24 Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller15.5.3 MMC_CLKRT Register (MMC_CLKRT)MMC_CLKRT, shown in Table 15-7, specif

Intel® PXA255 Processor Developer’s Manual 15-25 MultiMediaCard ControllerThis is a read/write register. Ignore reads from reserved bits. Write zeros

Intel® PXA255 Processor Developer’s Manual 2-23 System Architecture0x4000_024C DCMD4 DMA Command Address Register Channel 40x4000_0250 DDADR5 DMA Desc

15-26 Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller15.5.5 MMC_CMDAT Register (MMC_CMDAT)MMC_CMDAT, shown in Table 15-9, contr

Intel® PXA255 Processor Developer’s Manual 15-27 MultiMediaCard Controller15.5.6 MMC_RESTO Register (MMC_RESTO)The MMC_RESTO, shown in Table 15-10, co

15-28 Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller15.5.7 MMC_RDTO Register (MMC_RDTO)MMC_RDTO, shown in Table 15 -11, determi

Intel® PXA255 Processor Developer’s Manual 15-29 MultiMediaCard Controller15.5.8 MMC_BLKLEN Register (MMC_BLKLEN)MMC_BLKLEN, shown in Table 15-12, sp

15-30 Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller15.5.10 MMC_PRTBUF Register (MMC_PRTBUF)MMC_PRTBUF, shown in Table 15-14, i

Intel® PXA255 Processor Developer’s Manual 15-31 MultiMediaCard Controller15.5.12 MMC_I_REG Register (MMC_I_REG)MMC_I_REG, shown in Table 15-16, shows

15-32 Intel® PXA255 Processor Developer’s Manual MultiMediaCard ControllerTable 15-16. MMC_I_REG Bit DefinitionsPhysical Address0x4110_002cMMC_I_REG

Intel® PXA255 Processor Developer’s Manual 15-33 MultiMediaCard Controller15.5.13 MMC_CMD Register (MMC_CMD)MMC_CMD, shown in Table 15-17, specifies t

15-34 Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller010100 CMD20 MMC WRITE_DAT_UNTIL_STOP010101 CMD21 reserved010110 CMD22 rese

Intel® PXA255 Processor Developer’s Manual 15-35 MultiMediaCard Controller15.5.14 MMC_ARGH Register (MMC_ARGH)MMC_ARGH, shown in Table 15-19, specifie

2-24 Intel® PXA255 Processor Developer’s Manual System Architecture0x4000_02EC DCMD14 DMA Command Address Register Channel 140x4000_02F0 DDADR15 DMA

15-36 Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller15.5.16 MMC_RES FIFOMMC_RES FIFO, shown in Table 15 -21, contains the resp

Intel® PXA255 Processor Developer’s Manual 15-37 MultiMediaCard Controller15.5.18 MMC_TXFIFO FIFOMMC_TXFIFO, shown in Table 15-23, consists of two dua

15-38 Intel® PXA255 Processor Developer’s Manual MultiMediaCard Controller0x4110_003c MMC_RES Response FIFO (read only)0x4110_0040 MMC_RXFIFO Receive

Intel® PXA255 Processor Developer’s Manual 16-1Network SSP Serial Port 16This chapter describes the signal definitions and operation of the Intel® P

16-2 Intel® PXA255 Processor Developer’s Manual Network SSP Serial Port16.3 Signal DescriptionTable 16-1 lists the external signals between the SSP s

Intel® PXA255 Processor Developer’s Manual 16-3 Network SSP Serial PortThe FIFOs can also be accessed by DMA bursts (in multiples of one, two or fou

16-4 Intel® PXA255 Processor Developer’s Manual Network SSP Serial Port• SSPSCLK–Defines the bit rate at which serial data is driven onto and sampled

Intel® PXA255 Processor Developer’s Manual 16-5 Network SSP Serial Porttransmit data exist within the transmit FIFO. At other times, SSPSCLK holds i

16-6 Intel® PXA255 Processor Developer’s Manual Network SSP Serial Port16.4.3.2 SPI Protocol DetailsThe SPI protocol has four possible sub-modes, dep

Intel® PXA255 Processor Developer’s Manual 16-7 Network SSP Serial PortNote: When configured as either master or slave (to clock or frame) the SSP c

Intel® PXA255 Processor Developer’s Manual 2-25 System ArchitectureI2S 0x4040_00000x4040_0000 SACR0 Global Control Register0x4040_0004 SACR1 Serial Au

16-8 Intel® PXA255 Processor Developer’s Manual Network SSP Serial PortWhen SPH is set, SSPSCLK remains in its inactive or idle state (as determined

Intel® PXA255 Processor Developer’s Manual 16-9 Network SSP Serial PortSSPRXD is undefined before the MSB and after the LSB is transmitted. For mini

16-10 Intel® PXA255 Processor Developer’s Manual Network SSP Serial PortNote: When configured master the SSP continues to drive SSPTXD with the last

Intel® PXA255 Processor Developer’s Manual 16-11 Network SSP Serial Portclocks programmed in the field SSPSP[SFRMP]. The SSPSFRM remains asserted fo

16-12 Intel® PXA255 Processor Developer’s Manual Network SSP Serial PortNote: The SSPSFRM delay must not extend beyond the end of T4. SSPSFRM Width m

Intel® PXA255 Processor Developer’s Manual 16-13 Network SSP Serial Portset) if the assertion of frame is not before the MSB is sent (For example, T

16-14 Intel® PXA255 Processor Developer’s Manual Network SSP Serial PortNote: If SSPSCLK is an input, the device driving SSPSCLK must provide another

Intel® PXA255 Processor Developer’s Manual 16-15 Network SSP Serial PortNote: SSCR1[TTELP] must be 0 for National Semiconductor Microwire.16.4.4.4 P

16-16 Intel® PXA255 Processor Developer’s Manual Network SSP Serial PortSSCR1[TTELP] can only be set to 1 in PSP mode if the SSP is a slave to frame.

Intel® PXA255 Processor Developer’s Manual 16-17 Network SSP Serial Port16.4.5 FIFO OperationTwo separate and independent FIFOs are present for tran

2-26 Intel® PXA255 Processor Developer’s Manual System Architecture0x4050_0114 — Reserved0x4050_0118 MISR Modem In Status Register0x4050_011Cthrough0

16-18 Intel® PXA255 Processor Developer’s Manual Network SSP Serial Port16.5 Register DescriptionsEach SSP consists of seven registers: three control

Intel® PXA255 Processor Developer’s Manual 16-19 Network SSP Serial PortTable 16-3. SSCR0 Bit Definitions (Sheet 1 of 2)0x4140_0000 SSCR0 Network SS

16-20 Intel® PXA255 Processor Developer’s Manual Network SSP Serial Port16.5.2 SSP Control Register 1 (SSCR1)SSCR1, shown in Table 16-4, contains bit

Intel® PXA255 Processor Developer’s Manual 16-21 Network SSP Serial PortTable 16-4. SSCR1 Bit Definitions (Sheet 1 of 2)0x04140_0004 SSCR1 Network

16-22 Intel® PXA255 Processor Developer’s Manual Network SSP Serial Port16.5.3 SSP Programmable Serial Protocol Register (SSPSP)SSPSPx, shown in Tabl

Intel® PXA255 Processor Developer’s Manual 16-23 Network SSP Serial PortTable 16-5. SSPSP Bit Definitions (Sheet 1 of 2)0x4140_002C SSPSP Network SS

16-24 Intel® PXA255 Processor Developer’s Manual Network SSP Serial Port16.5.4 SSP Time Out Register (SSTO)The SSTO register, shown in Table 16-6,spe

Intel® PXA255 Processor Developer’s Manual 16-25 Network SSP Serial PortSetting any of these bits also causes the corresponding status bit(s) to be

16-26 Intel® PXA255 Processor Developer’s Manual Network SSP Serial PortBits that cause an interrupt signal the request as long as the bit is set. Th

Intel® PXA255 Processor Developer’s Manual 16-27 Network SSP Serial Port19 TINTRECEIVER TIME-OUT INTERRUPT:Indicates that the receive FIFO has been

Intel® PXA255 Processor Developer’s Manual 2-27 System Architecture0x4060_0068 UBCR2 UDC Byte Count Register 20x4060_006C UBCR4 UDC Byte Count Registe

16-28 Intel® PXA255 Processor Developer’s Manual Network SSP Serial Port16.5.7 SSP Data Register (SSDR)SSDR, shown in Table 16-9, is a single address

Intel® PXA255 Processor Developer’s Manual 16-29 Network SSP Serial PortAs the system accesses the register, FIFO control logic transfers data autom

16-30 Intel® PXA255 Processor Developer’s Manual Network SSP Serial Port

Intel® PXA255 Processor Developer’s Manual 17-1Hardware UART 17This chapter describes the signal definitions and operations of the PXA255 processor ha

17-2 Intel® PXA255 Processor Developer’s Manual Hardware UART— Non-Return-to-Zero (NRZ) encoding/decoding function— 64 byte transmit/receive FIFO buf

Intel® PXA255 Processor Developer’s Manual 17-3 Hardware UART17.3 Signal DescriptionsTable 17-1 lists and describes each external signal that is conne

17-4 Intel® PXA255 Processor Developer’s Manual Hardware UARTReceive data sample counter frequency is 16 times the value of the bit frequency. The 16

Intel® PXA255 Processor Developer’s Manual 17-5 Hardware UART17.4.2.1 FIFO Interrupt Mode Operation17.4.2.1.1 Receive InterruptFor a receive interrupt

17-6 Intel® PXA255 Processor Developer’s Manual Hardware UART17.4.2.3 FIFO DMA Mode OperationThe UART has two DMA requests: one for transmit data ser

Intel® PXA255 Processor Developer’s Manual 17-7 Hardware UARTNote: Ensure that the DMA controller has completed the previous receive DMA requests befo

2-28 Intel® PXA255 Processor Developer’s Manual System ArchitectureICP 0x4080_00000x4080_0000 ICCR0 ICP Control Register 00x4080_0004 ICCR1 ICP Contr

17-8 Intel® PXA255 Processor Developer’s Manual Hardware UARTIf the UART is to program the Divisor Latch registers, you can choose one of two methods

Intel® PXA255 Processor Developer’s Manual 17-9 Hardware UARTThe top line in Figure 17-3 shows an asynchronous transmission as it is sent from the UAR

17-10 Intel® PXA255 Processor Developer’s Manual Hardware UART17.5 Register Descriptions17.5.1 Receive Buffer Register (RBR)In non-FIFO mode, the RBR

Intel® PXA255 Processor Developer’s Manual 17-11 Hardware UARTLoad these divisor latches during initialization to ensure that the baud rate generator

17-12 Intel® PXA255 Processor Developer’s Manual Hardware UARTEnabling DMA requests also enables a separate error interrupt. For additional informati

Intel® PXA255 Processor Developer’s Manual 17-13 Hardware UART17.5.5 Interrupt Identification Register (IIR)The UART prioritizes interrupts in four le

17-14 Intel® PXA255 Processor Developer’s Manual Hardware UARTTable 17-9 shows the priority, type, and source of the Interrupt Identification registe

Intel® PXA255 Processor Developer’s Manual 17-15 Hardware UART17.5.6 FIFO Control Register (FCR)The FCR, shown in Table 17-10, is a write-only registe

17-16 Intel® PXA255 Processor Developer’s Manual Hardware UART17.5.7 Receive FIFO Occupancy Register (FOR)The FOR, shown in Table 17-11, shows the nu

Intel® PXA255 Processor Developer’s Manual 17-17 Hardware UART17.5.8 Auto-Baud Control Register (ABR)The ABR, shown in Table 17-12, controls the funct

Intel® PXA255 Processor Developer’s Manual 2-29 System Architecture0x40E0_0008 GPLR2 GPIO Pin-Level Register GPIO<80:64>0x40E0_000C GPDR0 GPIO P

17-18 Intel® PXA255 Processor Developer’s Manual Hardware UARTThis is a read-only register. Ignore reads from reserved bits.17.5.10 Line Control Regi

Intel® PXA255 Processor Developer’s Manual 17-19 Hardware UART17.5.11 Line Status Register (LSR)The LSR, shown in Table 17-15, provides data transfer

17-20 Intel® PXA255 Processor Developer’s Manual Hardware UARTTable 17-15. LSR Bit Definitions (Sheet 1 of 2)Physical Address0x4160_0014Line Status R

Intel® PXA255 Processor Developer’s Manual 17-21 Hardware UART17.5.12 Modem Control Register (MCR)The MCR, shown in Table 17-16, uses the modem contro

17-22 Intel® PXA255 Processor Developer’s Manual Hardware UARTTable 17-16. MCR Bit Definitions (Sheet 1 of 2)Physical Address0x4160_0010Modem Control

Intel® PXA255 Processor Developer’s Manual 17-23 Hardware UART17.5.13 Modem Status Register (MSR)The MSR, shown in Table 17-17, provides the current s

17-24 Intel® PXA255 Processor Developer’s Manual Hardware UART17.5.14 Scratchpad Register (SCR)The SCR, shown in Table 17-18, has no effect on the UA

Intel® PXA255 Processor Developer’s Manual 17-25 Hardware UART17.6 Hardware UART Register SummaryTable 17-20 contains the register addresses for the H

17-26 Intel® PXA255 Processor Developer’s Manual Hardware UART0x4160_0008 X HWIIR “Interrupt Identification Register (IIR)” (read only)0x4160_0008 X

Intel® PXA255 Processor Developer’s Manual 17-27 Hardware UART

vi Intel® PXA255 Processor Developer’s Manual Contents6.2.1 SDRAM Interface Overview...

2-30 Intel® PXA255 Processor Developer’s Manual System Architecture0x40F0_002C — Reserved0x40F0_0030 RCSR Reset Controller Status RegisterSSP 0x4100_

Intel® PXA255 Processor Developer’s Manual 2-31 System Architecture0x4140_002C NSSPSP NSSP Programmable Serial ProtocolHardware UART0x4160_00000x4160_

2-32 Intel® PXA255 Processor Developer’s Manual System Architecture0x4800_0000 MDCNFG SDRAM Configuration Register 00x4800_0004 MDREFR SDRAM Refresh

Intel® PXA255 Processor Developer’s Manual 3-1Clocks and Power Manager 3The Clocks and Power Manager for the PXA255 processor controls the clock frequ

3-2 Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager3.2 Power Manager IntroductionThe Clocks and Power Manager can place the proce

Intel® PXA255 Processor Developer’s Manual 3-3 Clocks and Power ManagerThe clocks manager also contains clock gating for power reduction.Figure 3-1 sh

3-4 Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager3.3.1 32.768 kHz OscillatorThe 32.768 kHz oscillator is a low power, low frequ

Intel® PXA255 Processor Developer’s Manual 3-5 Clocks and Power ManagerNote: These are the only supported frequency settings.3.3.4 95.85 MHz Periphera

3-6 Intel® PXA255 Processor Developer’s Manual Clocks and Power Managerkeep each unit’s clock frequency within the unit’s clock tolerance. If a cryst

Intel® PXA255 Processor Developer’s Manual 3-7 Clocks and Power Manager3.4.1.1 Invoking Hardware ResetHardware Reset is invoked when the nRESET pin is

Intel® PXA255 Processor Developer’s Manual vii Contents7.2.1 Enabling the Controller ...

3-8 Intel® PXA255 Processor Developer’s Manual Clocks and Power ManagerRefer to Table 2-6, “Pin & Signal Descriptions for the PXA255 Processor” f

Intel® PXA255 Processor Developer’s Manual 3-9 Clocks and Power Managerpreviously programmed values, so the processor enters and exits GPIO Reset with

3-10 Intel® PXA255 Processor Developer’s Manual Clocks and Power ManagerDo not confuse the CCLKCFG Register, which is in Coprocessor 14, with the CCC

Intel® PXA255 Processor Developer’s Manual 3-11 Clocks and Power Manager3.4.6.2 Behavior in Idle ModeIn Idle Mode the CPU clocks are stopped, but the

3-12 Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager1. Configure the Memory Controller to ensure SDRAM contents are maintained du

Intel® PXA255 Processor Developer’s Manual 3-13 Clocks and Power Manager3.4.7.4 Completing the Frequency Change SequenceThe Frequency Change Sequence

3-14 Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager• SDRAM is placed in self refresh before entering 33-MHz idle mode, because S

Intel® PXA255 Processor Developer’s Manual 3-15 Clocks and Power Manager3.4.8.3 Exiting 33-MHz Idle ModeThe 33-MHz idle mode exit procedure is the sam

3-16 Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager3.4.9.2 Preparing for Sleep ModeBefore Sleep Mode starts, software must take

Intel® PXA255 Processor Developer’s Manual 3-17 Clocks and Power ManagerIf the external voltage regulator is failing or the main battery is low or mis

viii Intel® PXA255 Processor Developer’s Manual Contents9.3 Functional Description ...

3-18 Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager7. The CPU clock stops and power is removed from the Core.8. PWR_EN is deasse

Intel® PXA255 Processor Developer’s Manual 3-19 Clocks and Power Manager2. The PWR_EN signal is asserted and the Power Manager waits for the external

3-20 Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager3.4.10 Power Mode SummaryTable 3-4 shows the actions that occur when a Power

Intel® PXA255 Processor Developer’s Manual 3-21 Clocks and Power Manager11 Deassert nRESET_OUT x x12Restart CPU clocks, enable interrupts xxxxxx1: Fau

3-22 Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager3.5 Power Manager RegistersThis section describes the 32-bit registers that c

Intel® PXA255 Processor Developer’s Manual 3-23 Clocks and Power Manager3.5.1 Power Manager Control Register (PMCR)The PMCR is used to select the mann

3-24 Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager3.5.2 Power Manager General Configuration Register (PCFR)The PCFR contains bi

Intel® PXA255 Processor Developer’s Manual 3-25 Clocks and Power Manager3.5.3 Power Manager Wake-Up Enable Register (PWER)Table 3-9 shows the location

3-26 Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager3.5.4 Power Manager Rising-Edge Detect Enable Register (PRER)The PRER, shown

Intel® PXA255 Processor Developer’s Manual 3-27 Clocks and Power Manager3.5.5 Power Manager Falling-Edge Detect Enable Register (PFER)The PFER, Table

Intel® PXA255 Processor Developer’s Manual ix Contents11 Fast Infrared Communication Port...

3-28 Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager3.5.6 Power Manager GPIO Edge Detect Status Register (PEDR)The PEDR, Table 3-

Intel® PXA255 Processor Developer’s Manual 3-29 Clocks and Power Manager3.5.7 Power Manager Sleep Status Register (PSSR)The PSSR, shown in Table 3-13,

3-30 Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager3.5.8 Power Manager Scratch Pad Register (PSPR)The PM contains a 32-bit regis

Intel® PXA255 Processor Developer’s Manual 3-31 Clocks and Power Manager3.5.9 Power Manager Fast Sleep Walk-up Configuration Register (PMFW)The PSPR,

3-32 Intel® PXA255 Processor Developer’s Manual Clocks and Power ManagerThis is a read/write register. Ignore reads from reserved bits. Write zeros t

Intel® PXA255 Processor Developer’s Manual 3-33 Clocks and Power Manager3.5.11 Reset Controller Status Register (RCSR)The CPU uses the RCSR, shown in

3-34 Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager3.6 Clocks Manager RegistersThe Clocks Manager contains three registers:• Cor

Intel® PXA255 Processor Developer’s Manual 3-35 Clocks and Power ManagerMemory frequency = 3.6864 MHz crystal freq. * crystal frequency to memory freq

3-36 Intel® PXA255 Processor Developer’s Manual Clocks and Power Manager3.6.2 Clock Enable Register (CKEN)CKEN, shown in Table 3-21, enables or disab

Intel® PXA255 Processor Developer’s Manual 3-37 Clocks and Power Manager8 CKEN8I2S Unit Clock Enable0 – Clock to the unit is disabled1 – Clock to the