Intel IXP43X Bedienungsanleitung
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- Seite / 86
- Inhaltsverzeichnis
- LESEZEICHEN
- IXP43X Product Line of 1
- Network Processors 1
- HDG April 2007 2
- Contents 3
- Revision History 7
- 1.0 Introduction 9
- 1.2 Related Documentation 10
- 1.3 Acronyms 10
- 1.4 Overview 11
- 1.5 Typical Applications 14
- 2.0 System Architecture 15
- Processors 16
- Intel® IXP43X Product 16
- Line of Network 16
- 3.1 Soft Fusible Features 17
- 3.2 DDRII/I SDRAM Interface 18
- 3.2.1 Signal Interface 19
- 3.3 Expansion Bus 21
- 3.3.3 8-Bit Device Interface 24
- 3.3.4 16-Bit Device Interface 25
- 8-Bit Device 26
- 16-Bit Device 26
- 3.4.1 Signal Interface 28
- 3.5 MII Interface 29
- 3.5.1 Signal Interface MII 30
- 3.5.2 Device Connection, MII 31
- 3.6 GPIO Interface 32
- 3.7 USB Interface 33
- 3.7.1 Signal Interface 34
- Host Device 36
- 3.8 UTOPIA Level 2 Interface 37
- 3.8.2 Device Connection 41
- 3.9.1 Signal Interface 42
- 3.9.2 Device Connection 42
- 3.10.1 Signal Interface 44
- 3.10.2 Device Connection 44
- 3.11.1 Signal Interface 46
- 3.11.3 PCI Option Interface 48
- 3.12 JTAG Interface 50
- 3.13 Input System Clock 51
- B4111-005 52
- Intel® IXP43X 52
- Product Line of 52
- Network 52
- Table 21. Power Supply 53
- 4.0 General PCB Guide 56
- 4.5 Stack-Up Selection 57
- •Inexpensive 57
- B2275-02 59
- 5.1 Overview 60
- 5.2 General Layout Guidelines 60
- Return Current 61
- B2266-01 62
- 25 mils min 62
- PBGA Package 63
- 5.2.4 USB V2.0 Considerations 64
- 5.2.5 Crosstalk 64
- 5.2.7 Trace Impedance 65
- 5.2.8 Power and Ground Plane 65
- 6.1 Electrical Interface 67
- 6.2 Topology 67
- 6.3 Clock Distribution 68
- 6.3.1 Trace Length Limits 69
- 6.3.2 Routing Guidelines 70
- 6.3.3 Signal Loading 70
- 7.0 DDRII / DDRI SDRAM 71
- DDR SDRAM 73
- Requirements 75
- Signal-Timing Analysis 76
- 7.3.2 Timing Relationships 79
- 7.3.3.1 Clock Group 82
- 7.3.3.3 Command Groups 85
Inhaltsverzeichnis
Document Number: 316844; Revision: 001USIntel® IXP43X Product Line of Network ProcessorsHardware Design GuidelinesApril 2007
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