Intel 80960HD Bedienungsanleitung

80960HA/HD/HT 32-Bit High-Performance Superscalar Processor DatasheetProduct Features 32-Bit Parallel Architecture—Load/Store Architecture—Sixteen 32

80960HA/HD/HT 10 DatasheetIn addition to expanded clock frequency options, the 80960Hx provides essential enhancements for an emerging class of high-

80960HA/HD/HT 100 Datasheet “BYPASS (1111),” & “EXTEST (0000),” & “SAMPLE (0001),” & “IDCODE (0010),” & “RUBIST (

80960HA/HD/HT Datasheet 101 “6 (BC_1, *, control, 1),” & “7 (BC_4, ONCEBAR, input, X),” & “8 (BC_4, BOFFBAR,

80960HA/HD/HT 102 Datasheet “41 (CBSC_1, D(31), bidir, X, 17, 1, Z),” & “42 (BC_4, BTERMBAR, input, X),” & “43 (BC_4, RE

80960HA/HD/HT Datasheet 103 “76 (BC_1, A(19), output3, X, 80, 1, Z),” & “77 (BC_1, A(18), output3, X, 80, 1, Z),” & “

80960HA/HD/HT 104 DatasheetThis page intentionally left blank.

80960HA/HD/HT Datasheet 11subsystems with minimum system complexity. To reduce the effect of wait states, the bus design is decoupled from the core.

80960HA/HD/HT 12 Datasheet2.2.6 Dual Programmable TimersThe processor provides two independent 32-bit timers, with four programmable clock rates. The

80960HA/HD/HT Datasheet 132.3 Instruction Set SummaryTable 4 summarizes the 80960Hx instruction set by logical groupings.Table 4. 80960Hx Instructio

80960HA/HD/HT 14 Datasheet3.0 Package InformationThis section describes the pins, pinouts and thermal characteristics for the 80960Hx in the 168-pin

80960HA/HD/HT Datasheet 153.1 Pin DescriptionsThis section defines the 80960Hx pins. Table 6 presents the legend for interpreting the pin description

80960HA/HD/HT 16 DatasheetTable 7. 80960Hx Processor Family Pin Descriptions (Sheet 1 of 4)Name Type DescriptionA31:2OH(Z)B(Z)R(Z)ADDRESS BUS carri

80960HA/HD/HT Datasheet 17SUPOH(Z)B(Z)R(1)SUPERVISOR ACCESS indicates whether the current bus access originates from a request issued while in superv

80960HA/HD/HT 18 DatasheetHOLDIS(L)HOLD REQUEST signals that an external agent requests access to the processor’s address, data, and control buses. W

80960HA/HD/HT Datasheet 19CLKIN ICLOCK INPUT provides the time base for the 80960Hx. All internal circuitry is synchronized to CLKIN. All input and o

2 DatasheetINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO

80960HA/HD/HT 20 Datasheet3.2 80960Hx Mechanical Data3.2.1 80960Hx PGA PinoutFigure 2 depicts the complete 80960Hx PGA pinout as viewed from the top

80960HA/HD/HT Datasheet 21Figure 3. 80960Hx 168-Pin PGA Pinout—View from Bottom (Pins Facing Up)D5 D7 D8 D9 D11 D12 D13 D15 D16 D17 D19 D21 D24 D25D

80960HA/HD/HT 22 DatasheetTable 8. 80960Hx 168-Pin PGA Pinout—Signal Name Order (Sheet 1 of 2)Signal NamePGA PinSignal NamePGA PinSignal NamePGA Pi

80960HA/HD/HT Datasheet 23VCCJ16 VCCPLL B10 VSSH3 VSSQ10VCCK2 VOLDET A5 VSSH15 VSSQ11VCCK16 VSS A1 VSSJ3 W/RS10VCCM2 VSSC4 VSSJ15 WAITS12VCCM16 VSSC7

80960HA/HD/HT 24 DatasheetTable 9. 80960Hx 168-Pin PGA Pinout—Pin Number Order (Sheet 1 of 2)PGA PinSignal NamePGA PinSignal NamePGA PinSignal Name

80960HA/HD/HT Datasheet 25Q4 D28 Q16 A21 R11 VCCS6 BE2Q5 D30 Q17 A18 R12 BSTALL S7 BE1Q6 VCCR1 D24 R13 BREQ S8 BLASTQ7 VSSR2 D27 R14 A29 S9 DENQ8 VSS

80960HA/HD/HT 26 Datasheet3.2.2 80960Hx PQ4 PinoutFigure 4. 80960Hx 208-Pin PQ4 PinoutPIN 1PIN 208PIN 52PIN 53PIN 104PIN 157PIN 156VCCVSSVSSVCCFAIL

80960HA/HD/HT Datasheet 27Table 10. 80960Hx PQ4 Pinout—Signal Name Order (Sheet 1 of 2)Signal NamePQ4 PinSignal NamePQ4 PinSignal NamePQ4 PinSignal

80960HA/HD/HT 28 DatasheetVCC92 VCC187 VSS70 VSS164VCC95 VCC196 VSS73 VSS170VCC101 VCC199 VSS75 VSS172VCC102 VCC201 VSS80 VSS178VCC109 VCC204 VSS86 V

80960HA/HD/HT Datasheet 29Table 11. 80960Hx PQ4 Pinout—Pin Number Order (Sheet 1 of 2)PQ4 PinSignal NamePQ4 PinSignal NamePQ4 PinSignal NamePQ4 Pin

Datasheet 3ContentsContents1.0 About This Document ...

80960HA/HD/HT 30 Datasheet121 A20 143 VCC165 VCC187 VCC122 VSS144 A7 166 XINT3188 TDO123 VCC145 A6 167 XINT2189 PCHK124 A19 146 A5 168 XINT1 190 VSS1

80960HA/HD/HT Datasheet 313.3 Package Thermal SpecificationsThe 80960Hx is specified for operation when TC (case temperature) is within the range of

80960HA/HD/HT 32 DatasheetTable 12. Maximum TA at Various Airflows in ° C (PGA Package Only)Airflow-ft/min (m/sec)fCLKIN (MHz)0(0)200(1.01)400(2.03)

80960HA/HD/HT Datasheet 33Table 14. Maximum TA at Various Airflows in ° C (PQ4 Package Only)Airflow-ft/min (m/sec)fCLKIN (MHz)0(0)200(1.01)400(2.03)

80960HA/HD/HT 34 Datasheet3.4 Heat Sink AdhesivesIntel recommends silicone-based adhesives to attach heat sinks to the PGA package. There is no parti

80960HA/HD/HT Datasheet 35Table 16. Fields of 80960Hx Device IDField Value DefinitionVersion See Table 18. Indicates major stepping changes. VCC1 =

80960HA/HD/HT 36 Datasheet3.7 Sources for AccessoriesThe following is a list of suggested sources for 80960Hx accessories. This is neither an endorse

80960HA/HD/HT Datasheet 374.0 Electrical Specifications4.1 Absolute Maximum RatingsWarning: Stressing the device beyond the “Absolute Maximum Ratings

80960HA/HD/HT 38 Datasheet4.3 Recommended ConnectionsPower and ground connections must be made to multiple VCC and VSS (GND) pins. Every 80960Hx-base

80960HA/HD/HT Datasheet 394.5 VCCPLL Pin RequirementsWhen the voltage on the VCCPLL power supply pin exceeds the VCC pin voltage by 0.5 V at any time

Contents4 Datasheet7 VCC5 Current-Limiting Resistor ...

80960HA/HD/HT 40 Datasheet4.6 D.C. SpecificationsTable 22. 80960Hx D.C. Characteristics (Sheet 1 of 2)Per the conditions described in Section 4.3, “

80960HA/HD/HT Datasheet 41ICC5 Current on the VCC5 Pin80960HA80960HD80960HT200200200µA9CINInput Capacitance for:PQ4 PGA1212pFpFFC = 1 MHz10COUTOutput

80960HA/HD/HT 42 Datasheet4.7 A.C. SpecificationsTable 23. 80960Hx A.C. Characteristics (Sheet 1 of 2)Per conditions in Section 4.2, “Operating Cond

80960HA/HD/HT Datasheet 43TIS2Input Setup for READY, BTERM, HOLD, and BOFF6nsTIH2Input Hold for READY, BTERM, HOLD, and BOFF2.5 nsRelative Output Tim

80960HA/HD/HT 44 DatasheetTable 24. A.C. Characteristics NotesNOTES:1. See Section 4.8, “AC Timing Waveforms” on page 46 for waveforms and definition

80960HA/HD/HT Datasheet 454.7.1 A.C. Test ConditionsA.C. values are derived using the 50 pF load shown in Figure 8. Figure 25, “Output Delay or Hold

80960HA/HD/HT 46 Datasheet4.8 A.C. Timing WaveformsFigure 9. CLKIN WaveformFigure 10. Output Delay WaveformFigure 11. Output Delay Waveform2.0 V1.5

80960HA/HD/HT Datasheet 47Figure 12. Output Float WaveformFigure 13. Input Setup and Hold WaveformFigure 14. NMI, XINT7:0 Input Setup and Hold Wavefo

80960HA/HD/HT 48 DatasheetFigure 15. Hold Acknowledge TimingsFigure 16. Bus Backoff (BOFF) TimingsCLKIN1.5 V1.5 V1.5 VHOLDTISTIH1.5 VTIHTISHOLDATOV1M

80960HA/HD/HT Datasheet 49Figure 17. TCK WaveformFigure 18. Input Setup and Hold Waveforms for TBSIS1 and TBSIH12.0 V1.5 V0.8 VTBSCFTBSCHTBSCLTBSCTBS

Datasheet 5Contents57 A Summary of Aligned and Unaligned Transfers for 8-Bit Bus...8158 Idle Bus Opera

80960HA/HD/HT 50 DatasheetFigure 19. Output Delay and Output Float for TBSOV1 and TBSOF1Figure 20. Output Delay and Output Float Waveform for TBSOV2

80960HA/HD/HT Datasheet 51Figure 22. Rise and Fall Time Derating at 85 ° C and Minimum VCCFigure 23. ICC Active (Power Supply) vs. Frequency50pF 100p

80960HA/HD/HT 52 DatasheetFigure 24. ICC Active (Thermal) vs. FrequencyFigure 25. Output Delay or Hold vs. Load CapacitanceICC Active (Thermal) (mA)C

80960HA/HD/HT Datasheet 53Figure 26. Output Delay vs. TemperatureFigure 27. Output Hold Times vs. TemperatureFigure 28. Output Delay vs. VCC nom - 0.

80960HA/HD/HT 54 Datasheet5.0 Bus WaveformsFigure 29. Cold Reset WaveformCLKINCT3:0, ADS,W/R, DT/R,D31:0,STESTRESETVCC, VCC5, LOCK, WAIT,DEN, BLASTBR

80960HA/HD/HT Datasheet 55Figure 30. Warm Reset Waveform∼∼∼∼∼∼∼∼Maximum RESET Low to RESET State16 CLKIN Periods1 CLKIN∼∼∼∼∼∼∼∼∼∼∼∼∼∼CLKINADS,DT/RSUP

80960HA/HD/HT 56 DatasheetFigure 31. Entering ONCE ModeCLKINADS, BE3:0, A31:2, RESETONCE∼∼∼∼∼∼∼∼∼∼∼∼∼∼∼∼∼∼∼∼∼∼∼∼CLKIN and VCC Stable and RESET low an

80960HA/HD/HT Datasheet 57Figure 32. Non-Burst, Non-Pipelined Requests without Wait StatesInADSA31:2, SUP,D/C,LOCK, CT3:0W/RBLASTDT/RDENWAITD31:0,CLK

80960HA/HD/HT 58 DatasheetFigure 33. Non-Burst, Non-Pipelined Read Request with Wait StatesADSA31:2, BE3:0W/RBLASTDT/RDENWAITD31:0,CLKINA321D1InValid

80960HA/HD/HT Datasheet 59Figure 34. Non-Burst, Non-Pipelined Write Request with Wait StatesADSA31:2,W/RBLASTDT/RDENWAITD31:0,CLKINA3 21 D1OutAValidV

Contents6 DatasheetRevision HistoryDate Revision HistorySeptember 2002 008Formatted the datasheet in a new template.In “32-Bit Parallel Architecture”

80960HA/HD/HT 60 DatasheetFigure 35. Burst, Non-Pipelined Read Request without Wait States, 32-Bit BusIn0ADSA31:4, SUP,CT3:0,D/C,BE3:0, LOCKW/RBLASTD

80960HA/HD/HT Datasheet 61Figure 36. Burst, Non-Pipelined Read Request with Wait States, 32-Bit BusADSA31:4, SUP,CT3:0, D/C,BE3:0, LOCKW/RBLASTDT/RDE

80960HA/HD/HT 62 DatasheetFigure 37. Burst, Non-Pipelined Write Request without Wait States, 32-Bit BusADSA31:4, SUP,CT3:0, D/C,BE3:0, LOCKW/RBLASTDT

80960HA/HD/HT Datasheet 63Figure 38. Burst, Non-Pipelined Write Request with Wait States, 32-Bit BusADSA31:4, SUP,CT3:0, D/C,BE3:0, LOCKW/RBLASTDT/RD

80960HA/HD/HT 64 DatasheetFigure 39. Burst, Non-Pipelined Read Request with Wait States, 16-Bit BusADSSUP, CT3:0,W/RBLASTDT/RDENA3:2WAITD31:0,CLKINA2

80960HA/HD/HT Datasheet 65Figure 40. Burst, Non-Pipelined Read Request with Wait States, 8-Bit BusADSSUP, CT3:0,W/RBLASTDT/RDENA3:2WAITD31:0,CLKINA21

80960HA/HD/HT 66 DatasheetFigure 41. Non-Burst, Pipelined Read Request without Wait States, 32-Bit BusADSA31:4, SUP,CT3:0, D/C,LOCKBLASTWAITD31:0,CLK

80960HA/HD/HT Datasheet 67Figure 42. Non-Burst, Pipelined Read Request with Wait States, 32-Bit BusADSA31:4, SUP,CT3:0, D/C,W/RBLASTDT/RDENA3:2WAITD3

80960HA/HD/HT 68 DatasheetFigure 43. Burst, Pipelined Read Request without Wait States, 32-Bit BusADSA31:4, SUP,CT3:0, D/C,BE3:0, LOCKW/RBLASTDT/RDEN

80960HA/HD/HT Datasheet 69Figure 44. Burst, Pipelined Read Request with Wait States, 32-Bit BusADSA31:4, SUP,CT3:0, D/C,BE3:0, LOCKW/RA3:2D31:0,WAITB

Datasheet 7ContentsJuly 1998 (continued)007 (continued)In Table 23 “80960Hx AC Characteristics” on page 42:• Added overbars where required.• Modified

80960HA/HD/HT 70 DatasheetFigure 45. Burst, Pipelined Read Request with Wait States, 8-Bit BusADSA31:4, SUP,CT3:0, D/C,LOCKW/RA3:2BE1/A1,WAITBLASTDT/

80960HA/HD/HT Datasheet 71Figure 46. Burst, Pipelined Read Request with Wait States, 16-Bit BusADSA31:4, SUP,CT3:0, D/C,BE0/BLC, W/RA3:2BE1/A1WAITBLA

80960HA/HD/HT 72 DatasheetFigure 47. Using External READYCLKINADSA31:4, SUP,DT/RDENREADYW/RCT3:0, D/C,BLASTBTERMA3:2WAITD31:0,BE3:0, LOCKD0 D1 D2 D3

80960HA/HD/HT Datasheet 73Figure 48. Terminating a Burst with BTERMCLKINADSA31:4, SUP,DT/RDENREADYW/RCT3:0, D/C,BLASTBTERMA3:2WAITD31:0,BE3:0, LOCKD0

80960HA/HD/HT 74 DatasheetThe processor may stall (BSTALL asserted) even with an empty bus queue (BREQ deasserted). Depending on the instruction stre

80960HA/HD/HT Datasheet 75Figure 50. BOFF Functional Timing. BOFF occurs during a burst or non-burst data cycle.ADSBLASTREADYBOFFA31:2, SUP,DP3:0 &am

80960HA/HD/HT 76 DatasheetFigure 51. HOLD Functional TimingWord Read RequestNRAD=1, NXDA=1Word ReadRequestNRAD=0,NXDA=0Hold State Hold StateCLKINADSA

80960HA/HD/HT Datasheet 77Figure 52. LOCK Delays HOLDA TimingFigure 53. FAIL Functional TimingCLKINADSBLASTHOLDHOLDALOCKW/RRESET FAIL 257,517 Cycles

80960HA/HD/HT 78 DatasheetFigure 54. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions04 81216202401 234 56One Double-Word Short-WordLo

80960HA/HD/HT Datasheet 79Figure 55. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions (Continued)04 8121620240123456Triple-WordLoad/St

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80960HA/HD/HT 80 DatasheetFigure 56. A Summary of Aligned and Unaligned Transfers for 16-Bit Bus04 81216202401234 56Byte OffsetWord OffsetDouble Word

80960HA/HD/HT Datasheet 81Figure 57. A Summary of Aligned and Unaligned Transfers for 8-Bit Bus04 81216202401234 56Byte OffsetWord OffsetShort8-Bit B

80960HA/HD/HT 82 DatasheetFigure 58. Idle Bus OperationCLKINADSA31:4, SUP, D/C, LOCKW/RBLASTDT/RDENA3:2WAITD31:0READY,BTERMWrite RequestNWAD=2, NXDA

80960HA/HD/HT Datasheet 83Figure 59. Bus StatesTi = IDLETh = HOLDTa = ADDRESSTd = DATATb = BOFF’edTaw= address to data waitTo = ONCETaTbTd1Taw2Trw4Td

80960HA/HD/HT 84 Datasheet5.1 80960Hx Boundary Scan ChainTable 26. 80960Hx Boundary Scan Chain (Sheet 1 of 4)# Boundary Scan Cell Cell Type Comment

80960HA/HD/HT Datasheet 85D21 BidirectionalD22 BidirectionalD23 BidirectionalD24 BidirectionalD25 BidirectionalD26 BidirectionalD27 BidirectionalD28

80960HA/HD/HT 86 DatasheetLOCKBAR OutputBREQ OutputA31 OutputA30 OutputA29 OutputA28 OutputA27 OutputA26 OutputA25 OutputA24 OutputA23 OutputA22 Outp

80960HA/HD/HT Datasheet 87XINT7BAR InputAppears as XINTBAR(7:0) in BSDL file.XINT6BAR InputXINT5BAR InputXINT4BAR InputXINT3BAR InputXINT2BAR InputXI

80960HA/HD/HT 88 Datasheet5.2 Boundary Scan Description Language ExampleThe Boundary-Scan Description Language (BSDL) for PGA Package Example, as sho

80960HA/HD/HT Datasheet 89-- Project code HA-- File **NOT** verified electrically-- -------------------------------------------------- Rev 0.7 18

80960HA/HD/HT Datasheet 91.0 About This DocumentThis document describes the parametric performance of Intel’s 80960Hx embedded superscalar microproce

80960HA/HD/HT 90 Datasheet SUPBAR : out bit; TCK : in bit; TDI : in bit; TDO : out

80960HA/HD/HT Datasheet 91“D : (E03, C02, D02, C01, E02, D01, F02, E01, F01,”&“ G01, H02, H01, J01, K01, L02, L01, M01, N01,”&“ N02, P01,

80960HA/HD/HT 92 Datasheetattribute Tap_Scan_In of TDI : signal is true;attribute Tap_Scan_Mode of TMS : signal is true;attribute Tap_Scan_

80960HA/HD/HT Datasheet 93 attribute Boundary_Cells of Ha_Processor: entity is “BC_4, BC_1, CBSC_1”; attribute Boundary_Length of Ha_Processor: e

80960HA/HD/HT 94 Datasheet “35 (CBSC_1, D(25), bidir, X, 17, 1, Z),” & “36 (CBSC_1, D(26), bidir, X, 17, 1, Z),”

80960HA/HD/HT Datasheet 95 “74 (BC_1, A(21), output3, X, 80, 1, Z),” & “75 (BC_1, A(20), output3, X, 80, 1, Z),” &am

80960HA/HD/HT 96 DatasheetExample 2. Boundary-Scan Description Language (BSDL) for PQ2Package Example (Sheet 1 of 8)-- Copyright Intel Corporation 1

80960HA/HD/HT Datasheet 97entity Ha_Processor is generic(PHYSICAL_PIN_MAP : string:= “PQ2”); port (A : out bit_vector(2 to 31);

80960HA/HD/HT 98 Datasheet VCC1 : linkage bit_vector(0 to 23); VCC2 : linkage bit_vector(0 to 23); VSS1 : link

80960HA/HD/HT Datasheet 99 “ONCEBAR : 6,”& “PCHKBAR : 189,”& “READYBAR : 68,”& “RESETBAR : 174,”& “STEST : 208,”& “SUPB