Intel Itanium 2 Processor Bedienungsanleitung

Intel® Itanium® 2 ProcessorIntel® Itanium® 2 Processor 1.66 GHz with 9 MB L3 CacheIntel® Itanium® 2 Processor 1.66 GHz with 6 MB L3 CacheIntel® Itaniu

10 Datasheet

100 Datasheet Signals ReferenceA.1.39 IGNNE# (I)IGNNE# is ignored in the Itanium 2 processor system environment.A.1.40 INIT# (I)The Initialization (IN

Datasheet 101Signals ReferenceA.1.44 LINT[1:0] (I)LINT[1:0] are local interrupt signals. These pins are disabled after RESET#. LINT[0] is typically s

102 Datasheet Signals ReferenceAll receiving agents observe the REQ[5:0]# signals to determine the transaction type and participate in the transaction

Datasheet 103Signals ReferenceA correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signal

104 Datasheet Signals ReferenceA.1.59 STBn[7:0]# and STBp[7:0]# (I/O)STBp[7:0]# and STBn[7:0]# (and DRDY#) are used to transfer data at the 2x transfe

Datasheet 105Signals ReferenceA.1.64 THRMALERT# (O)THRMALERT# is asserted when the measured temperature from the processor thermal diode equals or ex

106 Datasheet Signals ReferenceSBSY_C1# Low BCLKp DataSBSY_C2# Low BCLKp DataTDO High TCK TAPTHRMTRIP# Low Asynchronous ErrorTHRMALERT# Low Asynchrono

Datasheet 107Signals ReferenceTable A-14. Input/Output Signals (Single Driver)Name Active Level Clock Signal Group QualifiedA[49:3]# Low BCLKp Reques

108 Datasheet Signals Reference

Datasheet 111 Introduction1.1 OverviewThe Itanium 2 processor employs Explicitly Parallel Instruction Computing (EPIC) design concepts for a tighter c

12 DatasheetIntroduction1.3 Mixing Processors of Different Frequencies and Cache SizesAll Itanium 2 processors on the same system bus are required to

Datasheet 13Introduction1.6 Reference DocumentsThe reader of this specification should also be familiar with material and concepts presented in the fo

14 DatasheetIntroduction

Datasheet 152 Electrical SpecificationsThis chapter describes the electrical specifications of the Itanium 2 processor.2.1 Itanium® 2 Processor System

16 Datasheet Electrical Specifications..All system bus outputs should be treated as open drain signals and require a high level source provided by the

Datasheet 17Electrical SpecificationsVCTERMSystem bus termination voltage.GND System ground.N/C No connection can be made to these pins.TERMA, TERMB T

18 Datasheet Electrical Specifications2.4 Signal SpecificationsThis section describes the DC specifications of the system bus signals. The processor s

Datasheet 19Electrical SpecificationsILLeakage Current All ±100 µA5CAGTL+AGTL+ Pad Capacitance 900 MHz 3 pF61.0 GHz 3 pF61.3 GHz 1.5 pF61.4 GHz 1.5 p

2 Datasheet INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO

20 Datasheet Electrical SpecificationsTable 2-10 through Table 2-11 list the AC specifications for the Itanium 2 processor’s clock and SMBus (timing d

Datasheet 21Electrical SpecificationsTlowBCLKp Low Time 266 1.69 1.88 2.06 ns Figure 2-14Tperiod BCLKp Period 333 3.0 ns Figure 2-1TskewSystem Clock S

22 Datasheet Electrical Specifications2.4.1 Maximum RatingsTable 2-12 contains the Itanium 2 processor stress ratings. Functional operation at the abs

Datasheet 23Electrical Specifications2.5 System Bus Signal Quality Specifications and Measurement GuidelinesOvershoot (or undershoot) is the absolute

24 Datasheet Electrical Specifications2.5.2 Overshoot/Undershoot Pulse DurationPulse duration describes the total time an overshoot/undershoot event e

Datasheet 25Electrical SpecificationsNote: AF for the common clock AGTL+ signals is referenced to BCLKn, and BCLKp frequency. The wired-OR Signals (BI

26 Datasheet Electrical Specifications3. If multiple overshoots and/or multiple undershoots occur, measure the worst-case pulse duration for each magn

Datasheet 27Electrical SpecificationsTable 2-15. Itanium® 2 Processors (1.5 GHz/4 MB, 1.6 GHz) Source Synchronous AGTL+ Signal Group Time-Dependent Ov

28 Datasheet Electrical Specifications2.5.6 Wired-OR SignalsSystem bus signals must meet certain overshoot and undershoot requirements. The maximum ab

Datasheet 29Electrical SpecificationsTable 2-19. Itanium® 2 Processors (1.5 GHz/4 MB, 1.6 GHz) Wired-OR Signal Group (BINIT#, HIT#, HITM#, BNR#, TND#,

Datasheet 3Contents1 Introduction...

30 Datasheet Electrical Specifications2.6 Power Pod Connector SignalsPower delivery for the Itanium 2 processor is from a DC-DC converter called the “

Datasheet 31Electrical SpecificationsThe power pod provides a selectable output voltage controlled via multiple binary weighted Voltage Identification

32 Datasheet Electrical Specifications2.7 Itanium® 2 Processor System Bus Clock and Processor ClockingThe BCLKn and BCLKp inputs control the operating

Datasheet 33Electrical SpecificationsListed in Table 2-25 are the system bus ratios defined for the Itanium 2 processor. The Itanium 2 processor suppo

34 Datasheet Electrical SpecificationsWarm Reset Sequence:• PWRGOOD remains high throughout the entire sequence as power is already available and stab

Datasheet 35Electrical Specifications2.8 Recommended Connections for Unused PinsPins that are unused in an application environment (as opposed to test

36 Datasheet Electrical SpecificationsSystem Management Signals3.3V GNDSMA[2:0] N/CSMSC N/CSMSD N/CSMWP N/CTHRMALERT# H1, 4LVTTL Power Pod SignalsOUTE

Datasheet 373 Pinout SpecificationsThis chapter describes the Itanium 2 processor signals and pinout. Note: The pins labeled “N/C” must remain unconn

38 Datasheet Pinout SpecificationsTable 3-1 provides the Itanium 2 processor pin list in alphabetical order.Table 3-2 provides the Itanium 2 processor

Datasheet 39Pinout SpecificationsA040# AA40#/AB40# V24 IN/OUTA041# AA41#/AB41# W25 IN/OUTA042# AA42#/AB42# U23 IN/OUTA043# AA43#/AB43# Y24 IN/OUTA044

4 Datasheet 6.1.3 SMBus Device Addressing... 816.2 Processor Information ROM...

40 Datasheet Pinout SpecificationsD010# D10# E07 IN/OUTD011# D11# H02 IN/OUTD012# D12# H04 IN/OUTD013# D13# J03 IN/OUTD014# D14# G03 IN/OUTD015# D15#

Datasheet 41Pinout SpecificationsD051# D51# M12 IN/OUTD052# D52# L13 IN/OUTD053# D53# L09 IN/OUTD054# D54# P08 IN/OUTD055# D55# N13 IN/OUTD056# D56#

42 Datasheet Pinout SpecificationsD092# D92# R15 IN/OUTD093# D93# P16 IN/OUTD094# D94# T14 IN/OUTD095# D95# P18 IN/OUTD096# D96# E21 IN/OUTD097# D97#

Datasheet 43Pinout SpecificationsDEP01# DEP1# J05 IN/OUTDEP02# DEP2# T06 IN/OUTDEP03# DEP3# T04 IN/OUTDEP04# DEP4# J09 IN/OUTDEP05# DEP5# J11 IN/OUTD

44 Datasheet Pinout SpecificationsGND GND AB19 INGND GND AB21 INGND GND AB23 INGND GND AB25 INGND GND AC02 INGND GND AC24 INGND GND AD01 INGND GND AD0

Datasheet 45Pinout SpecificationsGND GND AG22 INGND GND AG24 INGND GND AH01 INGND GND B03 INGND GND B05 INGND GND B07 INGND GND B09 INGND GND B10 ING

46 Datasheet Pinout SpecificationsGND GND F01 INGND GND F03 INGND GND F05 INGND GND F07 INGND GND F09 INGND GND F11 INGND GND F13 INGND GND F15 INGND

Datasheet 47Pinout SpecificationsGND GND K19 INGND GND K21 INGND GND K23 INGND GND K25 INGND GND L02 INGND GND M01 INGND GND M03 INGND GND M05 INGND

48 Datasheet Pinout SpecificationsGND GND T13 INGND GND T15 INGND GND T17 INGND GND T19 INGND GND T21 INGND GND T23 INGND GND T25 INGND GND U04 INGND

Datasheet 49Pinout SpecificationsID1# IDA1#/IP1# AB02 INID2# IDA2#/DHIT# AC03 INID3# IDA3#/IDB3# AA03 INID4# IDA4#/IDB4# AD04 INID5# IDA5#/IDB5# AB04

Datasheet 5A.1.37 ID[9:0]# (I) ...99A.1.38 IDS# (I)...

50 Datasheet Pinout SpecificationsN/C K02N/C K12N/C K14N/C K24N/C U05N/C U11OUTEN OUTEN AF04 IN Power pod signalPMI# PMI# AE25 INPPODGD# PPODGD# AF20

Datasheet 51Pinout SpecificationsSTBP2# STBP2# E11 IN/OUTSTBP3# STBP3# M10 IN/OUTSTBP4# STBP4# E17 IN/OUTSTBP5# STBP5# M16 IN/OUTSTBP6# STBP6# E23 IN

52 Datasheet Pinout SpecificationsVCTERM VCTERM G04 INVCTERM VCTERM G08 INVCTERM VCTERM G12 INVCTERM VCTERM G16 INVCTERM VCTERM G20 INVCTERM VCTERM G2

Datasheet 53Pinout SpecificationsTable 3-2. Pin/Signal Information Sorted by Pin Location (Sheet 1 of 15)Pin NameSystem BusSignal NamePin LocationInp

54 Datasheet Pinout SpecificationsN/C B20GND GND B21 INSMSD SMSD B22 IN/OUT SMBus signalGND GND B23 INSMSC SMSC B24 IN SMBus signalGND GND B25 INVCTER

Datasheet 55Pinout SpecificationsGND GND D11 IND036# D36# D12 IN/OUTGND GND D13 IND065# D65# D14 IN/OUTGND GND D15 IND066# D66# D16 IN/OUTGND GND D17

56 Datasheet Pinout SpecificationsGND GND F03 INSTBN0# STBN0# F04 IN/OUTGND GND F05 IND006# D06# F06 IN/OUTGND GND F07 IND045# D45# F08 IN/OUTGND GND

Datasheet 57Pinout SpecificationsVCTERM VCTERM G24 IND107# D107# G25 IN/OUTD011# D11# H02 IN/OUTGND GND H03 IND012# D12# H04 IN/OUTGND GND H05 IND009

58 Datasheet Pinout SpecificationsGND GND J16 INDEP09# DEP9# J17 IN/OUTVCTERM VCTERM J18 INDEP08# DEP8# J19 IN/OUTGND GND J20 INDEP12# DEP12# J21 IN/O

Datasheet 59Pinout SpecificationsD053# D53# L09 IN/OUTD056# D56# L11 IN/OUTVCTERM VCTERM L12 IND052# D52# L13 IN/OUTD081# D81# L15 IN/OUTVCTERM VCTER

6 Datasheet 5-2 Itanium® 2 Processor Package Thermocouple Location... 776-1 Logical Schematic of SMBus Circuitry ...

60 Datasheet Pinout SpecificationsSTBN1# STBN1# N05 IN/OUTVCTERM VCTERM N06 IND022# D22# N07 IN/OUTD058# D58# N09 IN/OUTVCTERM VCTERM N10 INSTBN3# STB

Datasheet 61Pinout SpecificationsD120# D120# P24 IN/OUTGND GND P25 INVCTERM VCTERM R01 INGND GND R02 IND025# D25# R03 IN/OUTVCTERM VCTERM R04 IND029#

62 Datasheet Pinout SpecificationsDEP14# DEP14# T20 IN/OUTGND GND T21 INDEP15# DEP15# T22 IN/OUTGND GND T23 IND123# D123# T24 IN/OUTGND GND T25 INVCTE

Datasheet 63Pinout SpecificationsGND GND V15 INA038# AA38#/AB38# V16 IN/OUTGND GND V17 INA029# AA29#/xTPRValue2# V18 IN/OUTGND GND V19 INA045# AA45#/

64 Datasheet Pinout SpecificationsA035# AA35#/ATTR3# Y18 IN/OUTGND GND Y19 INA039# AA39#/AB39# Y20 IN/OUTGND GND Y21 INA049# AA49#/AB49# Y22 IN/OUTGND

Datasheet 65Pinout SpecificationsGND GND AB19 INADS# ADS# AB20 IN/OUTGND GND AB21 INBERR# BERR# AB22 IN/OUTGND GND AB23 INBPM5# BPM5# AB24 IN/OUTGND

66 Datasheet Pinout SpecificationsGND GND AD21 INBPM0# BPM0# AD22 IN/OUTGND GND AD23 INBPM4# BPM4# AD24 IN/OUTGND GND AD25 INGND GND AE02 INTERMB FSBT

Datasheet 67Pinout SpecificationsGND GND AG02 INTUNER[2] AG03GND GND AG04 INN/C AG05GND GND AG06 INTDI TDI AG07 IN JTAGGND GND AG08 INTCK TCK AG09 IN

68 Datasheet Pinout Specifications

Datasheet 694 Mechanical SpecificationsThis chapter provides the mechanical specifications of the Itanium 2 processor.4.1 Mechanical DimensionsThe It

Datasheet 76-2 Thermal Sensing Device SMBus Addressing on the Itanium® 2 Processor ...816-3 EEPROM SMBus Addressing on the Itanium® 2 Processor .

70 Datasheet Mechanical SpecificationsNOTE:Figure 4-2. Itanium® 2 Processor PackageAll dimensions are measured in mm. Not to scale.000655g90.0042.5038

Datasheet 71Mechanical SpecificationsFigure 4-3. Itanium® 2 Processor Package Power TabAll dimensions are measured in mm. Not to scale.001159aTop Vie

72 Datasheet Mechanical Specifications4.2 Package MarkingThe following section details the processor top-side and bottom-side markings for the Itanium

Datasheet 73Mechanical SpecificationsNOTE: 2D Matrix Mark only present on Itanium 2 processor (6 MB), Itanium 2 processor (4 MB) and Itanium 2 proces

74 Datasheet Mechanical Specifications

Datasheet 755 Thermal SpecificationsThis chapter provides a description of the thermal features relating to the Itanium 2 processor.5.1 Thermal Featu

76 Datasheet Thermal Specifications5.1.2 Enhanced Thermal ManagementETM is a new feature that has been added to the Itanium 2 processor. ETM uses a th

Datasheet 77Thermal SpecificationsFigure 5-2. Itanium® 2 Processor Package Thermocouple LocationAll dimensions are measured in mm. Not to scale.00110

78 Datasheet Thermal Specifications

Datasheet 796 System Management Feature SpecificationsThe Itanium 2 processor includes a system management bus (SMBus) interface. This chapter descri

8 Datasheet Revision HistoryRevision No. Description Date-001 Initial release of this document. July 2002-002 Updated content to include information p

80 Datasheet System Management Feature SpecificationsFigure 6-1. Logical Schematic of SMBus CircuitryNOTE:1. Actual implementation may vary.2. For use

Datasheet 81System Management Feature Specifications6.1.3 SMBus Device AddressingOf the addresses broadcast across the SMBus, the memory components c

82 Datasheet System Management Feature Specifications6.2 Processor Information ROMAn electrically programmed read-only memory (ROM) provides informati

Datasheet 83System Management Feature Specifications09h 8 Feature Data Address Byte pointer, 00h if not present 67h0Ah 8 Other Data Address Byte poin

84 Datasheet System Management Feature SpecificationsPackage37h 32 Package Revision Four 8-bit ASCII characters Itanium® 2 Package = INT2b, (1.50 GHz

Datasheet 85System Management Feature Specifications6.3 Scratch EEPROMAlso available on the SMBus interface on the processor is an EEPROM which may b

86 Datasheet System Management Feature Specificationscontroller continues to transmit data bytes until it terminates the sequence with a stop. All dat

Datasheet 87System Management Feature SpecificationsTHRMALERT# signal (see Section 6.1.1 for more details). At power up, the appropriate alarm regist

88 Datasheet System Management Feature SpecificationsAll of the commands are for reading or writing registers in the thermal sensor except the one-sho

Datasheet 89System Management Feature Specifications6.7.2 Thermal Limit RegistersThe thermal sensing device has two thermal limit registers; they def

Datasheet 9Intel® Itanium® 2 ProcessorIntel® Itanium® 2 Processor 1.66 GHz with 9 MB L3 CacheIntel® Itanium® 2 Processor 1.66 GHz with 6 MB L3 CacheI

90 Datasheet System Management Feature Specifications6.7.5 Conversion Rate RegisterThe contents of the conversion rate register determine the nominal

Datasheet 91A Signals ReferenceThis appendix provides an alphabetical listing of all Itanium 2 processor system bus signals. The tables at the end of

92 Datasheet Signals ReferenceAny memory access transaction addressing a memory region that is less than 64 GB (that is, Aa[49:36]# are all zeroes) mu

Datasheet 93Signals ReferenceFor memory or I/O transactions, the byte-enable signals indicate that valid data is requested or being transferred on th

94 Datasheet Signals ReferenceA.1.10 BINIT# (I/O)If enabled by configuration, the Bus Initialization (BINIT#) signal is asserted to signal any bus con

Datasheet 95Signals ReferenceDuring power-on configuration, the priority agent must assert the BR[0]# bus signal. All symmetric agents sample their B

96 Datasheet Signals Referencesampling BREQn# asserted by another symmetric agent, the symmetric owner deasserts BREQn# as soon as possible to release

Datasheet 97Signals ReferenceA.1.22 DBSY_C2# (O)DBSY# is a copy of the Data Bus Busy signal. This copy of the Data Bus Busy signal (DBSY_C2#) is an o

98 Datasheet Signals ReferenceThe Deferred Reply agent transmits the DID[9:0]# (Ab[25:16]#) signals received during the original transaction on the Aa

Datasheet 99Signals ReferenceA.1.33 FCL# (I/O)The Flush Cache Line (FCL#) signal is driven to the bus on the second clock of the Request Phase on the