Intel AT80569KJ073N Datenblatt

Document Number: 319005-002Quad-Core Intel® Xeon® Processor3300 SeriesDatasheetFebruary 2009Version -002

Introduction10 Datasheet1.1.1 Processor Terminology DefinitionsCommonly used terms are explained here for clarification:• Quad-Core Intel® Xeon® Proce

Boxed Processor Specifications100 DatasheetIf the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard CPU fan header it w

Datasheet101Debug Tools Specifications8 Debug Tools SpecificationsRefer to the Debug Port Design Guide for UP / DP Systems and the appropriate platfor

Debug Tools Specifications102 Datasheet

Datasheet11Introductionsolutions and enables more robust hardware assisted virtualization solutions. More information can be found at: http://www.inte

Introduction12 Datasheet

Datasheet13Electrical Specifications2 Electrical Specifications2.1 Power and Ground LandsThe processor has VCC (power), VTT, and VSS (ground) inputs f

Electrical Specifications14 Datasheetproperly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the mothe

Datasheet15Electrical Specifications00001110 1.525 01101010 0.95000100001.5125 011011000.937500010010 1.5 01101110 0.925000101001.4875 011100000.91250

Electrical Specifications16 Datasheet2.4 Reserved, Unused, and TESTHI SignalsAll RESERVED lands must remain unconnected. Connection of these lands to

Datasheet17Electrical Specifications2.6 Power Segment Identifier (PSID)Power Segment Identifier (PSID) is a mechanism to prevent booting under mismatc

Electrical Specifications18 DatasheetStorage within these limits will not affect the long-term reliability of the device. For functional operation, re

Datasheet19Electrical Specificationsdifferent settings within the VID range. Note that this differs from the VID employed by the processor during a po

2 DatasheetINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO A

Electrical Specifications20 DatasheetNOTES:1. The loadline specification includes both static and transient limits except for overshoot allowed as sho

Datasheet21Electrical Specifications3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulati

Electrical Specifications22 Datasheet2.7.4 Die Voltage ValidationOvershoot events on processor must meet the specifications in Table 2-5 when measured

Datasheet23Electrical SpecificationsNOTES:1. Refer to Section 4.2 for signal descriptions.2. In processor systems where no debug port is implemented o

Electrical Specifications24 Datasheet.NOTES:1. Signals that do not have RTT, nor are actively driven to their high-voltage level. NOTE:1. See Table 2-

Datasheet25Electrical SpecificationsNOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. VIL is def

Electrical Specifications26 Datasheet3. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.4. VI

Datasheet27Electrical SpecificationsValid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF.

Electrical Specifications28 Datasheet2.9 Clock Specifications2.9.1 Front Side Bus Clock (BCLK[1:0]) and Processor ClockingBCLK[1:0] directly controls

Datasheet29Electrical SpecificationsThe Yorkfield processor will operate at a 1333 MHz FSB frequency (selected by a 333 MHz BCLK[1:0] frequency). Indi

Datasheet 3Contents1Introduction...91.1 Ter

Electrical Specifications30 Datasheet2.9.4 BCLK[1:0] SpecificationsNOTES:1. Unless otherwise noted, all specifications in this table apply to all proc

Datasheet31Electrical Specifications7. Duty Cycle (High time/Period) must be between 40 and 60%.§Figure 2-3. Differential Clock WaveformThresholdRegio

Electrical Specifications32 Datasheet

Datasheet33Package Mechanical Specifications3 Package Mechanical Specifications3.1 Package Mechanical SpecificationsThe processor is packaged in a Fli

Package Mechanical Specifications34 Datasheet3.1.1 Package Mechanical DrawingThe package mechanical drawings are shown in Figure 3-2 and Figure 3-3. T

Datasheet35Package Mechanical SpecificationsFigure 3-2. Processor Package Drawing Sheet 1 of 3

Package Mechanical Specifications36 DatasheetFigure 3-3. Processor Package Drawing Sheet 2 of 3

Datasheet37Package Mechanical SpecificationsFigure 3-4. Processor Package Drawing Sheet 3 of 3

Package Mechanical Specifications38 Datasheet3.1.2 Processor Component Keep-Out ZonesThe processor may contain components on the substrate that define

Datasheet39Package Mechanical Specifications4. These guidelines are based on limited testing for design characterization. 3.1.5 Package Insertion Spec

4 Datasheet5.2 Processor Thermal Features ...805.2.1 Thermal Monitor ...

Package Mechanical Specifications40 Datasheet3.1.9 Processor Land CoordinatesFigure 3-6 shows the top view of the processor land coordinates. The coor

Datasheet41Land Listing and Signal Descriptions4 Land Listing and Signal DescriptionsThis chapter provides the processor land assignment and signal de

Land Listing and Signal Descriptions42 DatasheetFigure 4-1.land-out Diagram (Top View – Left Side)30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15ANVCC

Datasheet43Land Listing and Signal DescriptionsFigure 4-2.land-out Diagram (Top View – Right Side)14 13 12 11 10 9 8 7 6 5 4 3 2 1VCC VSS VCC VCC VSS

Land Listing and Signal Descriptions44 DatasheetTable 4-1. Alphabetical Land AssignmentsLand Name Land #Signal Buffer TypeDirectionA10# U6 Source Sync

Land Listing and Signal DescriptionsDatasheet45D25# D13 Source Synch Input/OutputD26# E13 Source Synch Input/OutputD27# G13 Source Synch Input/OutputD

Land Listing and Signal Descriptions46 DatasheetFC32 H15 Power/OtherFC33 H16 Power/OtherFC34 J17 Power/OtherFC35 H4 Power/OtherFC36 AD3 Power/OtherFC3

Land Listing and Signal DescriptionsDatasheet47TRDY# E3 Common Clock InputTRST# AG1 TAP InputVCC AA8 Power/Other VCC AB8 Power/Other VCC AC23 Power/

Land Listing and Signal Descriptions48 DatasheetVCC AJ18 Power/Other VCC AJ19 Power/Other VCC AJ21 Power/Other VCC AJ22 Power/Other VCC AJ25 Power

Land Listing and Signal DescriptionsDatasheet49VCC J28 Power/Other VCC J29 Power/Other VCC J30 Power/Other VCC J8 Power/Other VCC J9 Power/Other

Datasheet 53-6 Processor Land Coordinates and Quadrants, Top View...404-1 land-out Diagram (Top View – Lef

Land Listing and Signal Descriptions50 DatasheetVID0 AM2 Asynch CMOS OutputVID1 AL5 Asynch CMOS OutputVID2 AM3 Asynch CMOS OutputVID3 AL6 Asynch CMOS

Land Listing and Signal DescriptionsDatasheet51VSS AF30 Power/Other VSS AF6 Power/Other VSS AF7 Power/Other VSS AG10 Power/Other VSS AG13 Power/Ot

Land Listing and Signal Descriptions52 DatasheetVSS AN24 Power/Other VSS AN27 Power/Other VSS AN28 Power/Other VSS C10 Power/Other VSS C13 Power/O

Land Listing and Signal DescriptionsDatasheet53VSS N6 Power/Other VSS N7 Power/Other VSS P23 Power/Other VSS P24 Power/Other VSS P25 Power/Other

Land Listing and Signal Descriptions54 DatasheetTable 4-2. Numerical Land AssignmentLand #Land NameSignal Buffer TypeDirectionA10 D08# Source Synch In

Land Listing and Signal DescriptionsDatasheet55AD2 BPM2# Common Clock Input/OutputAD23 VCC Power/Other AD24 VCC Power/Other AD25 VCC Power/Other AD

Land Listing and Signal Descriptions56 DatasheetAG12 VCC Power/Other AG13 VSS Power/Other AG14 VCC Power/Other AG15 VCC Power/Other AG16 VSS Power

Land Listing and Signal DescriptionsDatasheet57AJ29 VSS Power/Other AJ3 ITP_CLK1 TAP InputAJ30 VSS Power/Other AJ4 VSS Power/Other AJ5 A34# Source

Land Listing and Signal Descriptions58 DatasheetAM18 VCC Power/Other AM19 VCC Power/Other AM2 VID0 Asynch CMOS OutputAM20 VSS Power/Other AM21 VCC

Land Listing and Signal DescriptionsDatasheet59B6 D05# Source Synch Input/OutputB7 D06# Source Synch Input/OutputB8 VSS Power/Other B9 DSTBP0# Source

6 DatasheetRevision HistoryDocument NumberVersion NumberRevision DescriptionRevision Date319005 1.0 -001 • Initial releaseJanuary 2008-002• Added Quad

Land Listing and Signal Descriptions60 DatasheetE23 RESERVED E24 FC10 Power/Other E25 VSS Power/Other E26 VSS Power/Other E27 VSS Power/Other E

Land Listing and Signal DescriptionsDatasheet61H15 FC32 Power/OtherH16 FC33 Power/OtherH17 VSS Power/Other H18 VSS Power/Other H19 VSS Power/Other

Land Listing and Signal Descriptions62 DatasheetL29 VSS Power/Other L3 VSS Power/Other L30 VSS Power/Other L4 A06# Source Synch Input/OutputL5 A03#

Land Listing and Signal DescriptionsDatasheet63T27 VCC Power/Other T28 VCC Power/Other T29 VCC Power/Other T3 VSS Power/Other T30 VCC Power/Other

Land Listing and Signal Descriptions64 Datasheet4.2 Alphabetical Signals ReferenceTable 4-3. Signal Description (Sheet 1 of 10)Name Type DescriptionA

Datasheet65Land Listing and Signal DescriptionsBPM[5:0]#BPMb[3:0]#Input/OutputBPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint and perform

Land Listing and Signal Descriptions66 DatasheetD[63:0]#Input/OutputD[63:0]# (Data) are the data signals. These signals provide a 64-bit data path bet

Datasheet67Land Listing and Signal DescriptionsDEFER# InputDEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order co

Land Listing and Signal Descriptions68 DatasheetFCx OtherFC signals are signals that are available for compatibility with other processors. Refer to t

Datasheet69Land Listing and Signal DescriptionsINIT# InputINIT# (Initialization), when asserted, resets integer registers inside the processor without

Datasheet 7Quad-Core Intel® Xeon® Processor 3300 Series FeaturesThe Quad-Core Intel® Xeon® Processor 3300 Series deliver Intel's advanced, powerf

Land Listing and Signal Descriptions70 DatasheetPWRGOOD InputPWRGOOD (Power Good) is a processor input. The processor requires this signal to be a cle

Datasheet71Land Listing and Signal DescriptionsSTPCLK# InputSTPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant

Land Listing and Signal Descriptions72 DatasheetVCC InputVCC are the power pins for the processor. The voltage supplied to these pins is determined by

Datasheet73Land Listing and Signal Descriptions§VTT_OUT_LEFTVTT_OUT_RIGHTOutputThe VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a vo

Land Listing and Signal Descriptions74 Datasheet

Datasheet75Thermal Specifications and Design Considerations5 Thermal Specifications and Design Considerations5.1 Processor Thermal SpecificationsThe p

Thermal Specifications and Design Considerations76 DatasheetThe case temperature is defined at the geometric top center of the processor. Analysis ind

Datasheet77Thermal Specifications and Design ConsiderationsTable 5-2. Quad-Core Intel® Xeon® Processor 3300 Series Thermal Profile (95W)Power (W) Max

Thermal Specifications and Design Considerations78 DatasheetFigure 5-1. Quad-Core Intel® Xeon® Processor 3300 Series Thermal Profile(95W)y = 0.28x + 4

Datasheet79Thermal Specifications and Design ConsiderationsTable 5-3. Quad-Core Intel® Xeon® Processor 3300 Series Thermal Profile (65W)Figure 5-2. Q

8 Datasheet

Thermal Specifications and Design Considerations80 Datasheet5.1.2 Thermal MetrologyThe maximum and minimum case temperatures (TC) for the processor is

Datasheet81Thermal Specifications and Design Considerationsperiods of TCC activation is expected to be so minor that it would be immeasurable. An unde

Thermal Specifications and Design Considerations82 DatasheetThe PROCHOT# signal is asserted when a high temperature situation is detected, regardless

Datasheet83Thermal Specifications and Design Considerations5.2.4 PROCHOT# SignalAn external signal, PROCHOT# (processor hot), is asserted when the pro

Thermal Specifications and Design Considerations84 Datasheet5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems Fan speed control solutions base

Datasheet85Thermal Specifications and Design Considerationsthat fall under the specification, the PECI will always respond to requests and the protoco

Thermal Specifications and Design Considerations86 Datasheet

Datasheet87Features6 Features6.1 Power-On Configuration OptionsSeveral configuration options can be configured by hardware. The processor samples the

Features88 Datasheet6.2.1 Normal StateThis is the normal operating state for the processor.6.2.2 HALT and Extended HALT Powerdown StatesThe processor

Datasheet89FeaturesThe system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# interr

Datasheet9Introduction1 IntroductionThe Quad-Core Intel® Xeon® Processor 3300 Series, like the Quad-Core Intel® Xeon® Processor 3200 Series, is a base

Features90 Datasheet6.2.4.1 HALT Snoop State, Stop Grant Snoop StateThe processor will respond to snoop transactions on the FSB while in Stop-Grant st

Datasheet91Boxed Processor Specifications7 Boxed Processor Specifications7.1 IntroductionThe processor will also be offered as an Intel boxed processo

Boxed Processor Specifications92 Datasheet7.2 Mechanical Specifications7.2.1 Boxed Processor Cooling Solution DimensionsThis section documents the mec

Datasheet93Boxed Processor SpecificationsNOTES:1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical

Boxed Processor Specifications94 Datasheet7.2.2 Boxed Processor Fan Heatsink WeightThe boxed processor fan heatsink will not weigh more than 450 grams

Datasheet95Boxed Processor SpecificationsFigure 7-5. Boxed Processor Fan Heatsink Power Cable Connector DescriptionTable 7-1. Fan Heatsink Power and S

Boxed Processor Specifications96 Datasheet7.4 Thermal SpecificationsThis section describes the cooling requirements of the fan heatsink solution utili

Datasheet97Boxed Processor Specifications Figure 7-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)

Boxed Processor Specifications98 Datasheet7.4.2 Variable Speed FanIf the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherbo

Datasheet99Boxed Processor SpecificationsIf the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the mother