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Datasheet, Volume 1 109

DDR Data Swizzling

9 DDR Data Swizzling

To achieve better memory performance and timing, Intel Design performed DDR Data

pin swizzling that allows a better use of the product across different platforms.

Swizzling has no effect on functional operation and is invisible to the operating

system/software.

However, during debug, swizzling needs to be taken into consideration. Therefore,

swizzling information is presented in this chapter. When placing a DIMM logic analyzer,

the design engineer must pay attention to the swizzling table in order to be able to

debug memory efficiently.

1 2 ... 104 105 106 107 108 109 110 111 112

Datasheet – Volume 1 of 2 1
Contents 3
Datasheet, Volume 1 4
Datasheet, Volume 1 5 5
Datasheet, Volume 1 7 7
Revision History 8
1 Introduction 9
Processor 10
1.1 Processor Feature Details 11
1.2 Interfaces 11
1.2.2 PCI Express* 12
Datasheet, Volume 1 13 13
Introduction 13
1.2.5 Processor Graphics 14
1.3 Power Management Support 15
1.4 Processor SKU Definitions 16
1.5 Package 17
1.6 Processor Compatibility 18
1.7 Terminology 19
1.8 Related Documents 22
2 Interfaces 23
2.1.3.1 Single-Channel Mode 25
Flex Memory Technology Mode 25
Interfaces 26
26 Datasheet, Volume 1 26
2.1.5.2 Command Overlap 27
2.2 PCI Express* Interface 28
2.2.1.1 Transaction Layer 29
2.2.1.2 Data Link Layer 29
2.2.1.3 Physical Layer 29
30 Datasheet, Volume 1 30
2.2.3 PCI Express* Port 31
2.3.1 DMI Error Flow 32
2.3.3 DMI Link Down 32
Datasheet, Volume 1 33 33
Interfaces 33
2.4.1.2 3D Pipeline 34
2.4.1.3 Video Engine 34
2.4.1.4 2D Engine 35
2.4.2.1 Display Planes 36
2.4.2.2 Display Pipes 37
2.4.2.3 Display Ports 37
2.6 Interface Clocking 38
3 Technologies 39
Technologies 40
40 Datasheet, Volume 1 40
Datasheet, Volume 1 41 41
Technologies 41
42 Datasheet, Volume 1 42
3.4 Intel 43
Turbo Boost Technology 43
3.5 Intel 44
3.7 Intel 45
64 Architecture x2APIC 45
46 Datasheet, Volume 1 46
4 Power Management 47
(ACPI) States Supported 48
4.2.1 Enhanced Intel 50
SpeedStep 50
Technology 50
4.2.2 Low-Power Idle States 50
C1 C1E C6C3 51
4.2.4.1 Core C0 State 52
4.2.4.2 Core C1 / C1E State 53
4.2.4.3 Core C3 State 53
4.2.4.4 Core C6 State 53
4.2.4.5 C-State Auto-Demotion 53
4.2.5 Package C-States 54
4.2.5.1 Package C0 55
4.2.5.2 Package C1/C1E 55
4.2.5.3 Package C3 State 56
4.2.5.4 Package C6 State 56
Management 56
Datasheet, Volume 1 57 57
Power Management 57
Power Management 58
58 Datasheet, Volume 1 58
Datasheet, Volume 1 59 59
4.5 DMI Power Management 60
4.6 Graphics Power Management 60
4.6.4 Intel 61
4.6.5 Intel 61
Graphics Dynamic Frequency 61
62 Datasheet, Volume 1 62
5 Thermal Management 63
Thermal Management 64
64 Datasheet, Volume 1 64
6 Signal Description 65
6.5 Intel 69
Flexible Display (Intel 69
FDI) Interface 69
6.10 Power Sequencing Signals 72
6.11 Processor Power Signals 73
6.12 Sense Signals 73
7 Electrical Specifications 75
Voltage Identification (VID) 76
7.5 System Agent (SA) V 80
7.7 Signal Groups 80
7.10 DC Specifications 84
(Sheet 2 of 2) 85
Specifications 86
DC Specifications 90
Electrical Specifications 92
92 Datasheet, Volume 1 92
8 Processor Land and Signal 93
94 Datasheet, Volume 1 94
Land Name 100
108 Datasheet, Volume 1 108
9 DDR Data Swizzling 109
Table – Channel A 110
112 Datasheet, Volume 1 112
DDR Data Swizzling 112

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