Intel LE80537VE001512 Datenblatt

Document Number: 317667-006 Intel® Celeron® Processor 500 Series Specification Update For Platforms Based on Mobile Intel® 965 Express Chips

Summary Tables of Changes 10 Specification Update Note: Each Specification Update item is prefixed with a capital letter to distinguish the pr

Summary Tables of Changes Specification Update 11 AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 Quad processor

Summary Tables of Changes 12 Specification Update Stepping Stepping Number A1 E1 Plans ERRATA AR1 X X No Fix Writing the Local Vector Table (L

Summary Tables of Changes Specification Update 13 Stepping Stepping Number A1 E1 Plans ERRATA AR21 X Fixed Sequential Code Fetch to Non-canonic

Summary Tables of Changes 14 Specification Update Stepping Stepping Number A1 E1 Plans ERRATA AR41 X Fixed Concurrent Multi-processor Writes to

Summary Tables of Changes Specification Update 15 Stepping Stepping Number A1 E1 Plans ERRATA AR64 X X No Fix PMI May Be Delayed to Next PEBS

Summary Tables of Changes 16 Specification Update Stepping Stepping Number A1 E1 Plans ERRATA AR86 X X No Fix Performance Monitoring Event SIMD_

Summary Tables of Changes Specification Update 17 Number SPECIFICATION CHANGES There are no Specification Changes in this Specification Update

Errata 18 Specification Update Errata AR1. Writing the Local Vector Table (LVT) When an Interrupt Is Pending May Cause an Unexpected Interrupt

Errata Specification Update 19 AR4. VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (LER) MSR Problem: The LER

2 Specification Update INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,

Errata 20 Specification Update AR7. General Protection Fault (#GP) for Instructions Greater Than 15 Bytes May Be Preempted Problem: When the p

Errata Specification Update 21 AR10. A Write to an APIC Register Sometimes May Appear to Have Not Occurred Problem: With respect to the retirem

Errata 22 Specification Update AR13. LER MSRs May Be Incorrectly Updated Problem: The LER (Last Exception Record) MSRs, MSR_LER_FROM_LIP (1DDH

Errata Specification Update 23 AR15. Performance Monitoring Event for Number of Reference Cycles When the Processor Is Not Halted (3CH) Does Not

Errata 24 Specification Update AR17. Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a

Errata Specification Update 25 AR19. FP Inexact-Result Exception Flag May Not Be Set Problem: When the result of a floating-point operation is

Errata 26 Specification Update AR20 Global Pages in the Data Translation Look-Aside Buffer (DTLB) May Not Be Flushed by RSM instruction before

Errata Specification Update 27 AR22. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Typ

Errata 28 Specification Update AR24. Premature Execution of a Load Operation Prior to Exception Handler Invocation Problem: If any of the belo

Errata Specification Update 29 AR26. EIP May Be Incorrect after Shutdown in IA-32e Mode Problem: When the processor is going into shutdown stat

Specification Update 3 Contents Preface ...

Errata 30 Specification Update AR29. Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate P

Errata Specification Update 31 AR31. Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction Execution Results Problem:

Errata 32 Specification Update AR33. Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update Problem:

Errata Specification Update 33 AR36. FXSAVE/FXRSTOR Instructions Which Store to the End of the Segment and Cause a Wrap to a Misaligned Base Add

Errata 34 Specification Update AR38. PREFETCHh Instruction Execution under Some Conditions May Lead to Processor Livelock Problem: PREFETCHh i

Errata Specification Update 35 AR41. Concurrent Multi-processor Writes to Non-dirty Page May Result in Unpredictable Behavior Problem: When a l

Errata 36 Specification Update AR44. SYSCALL Immediately after Changing EFLAGS.TF May Not Behave According to the New EFLAGS.TF Problem: If a

Errata Specification Update 37 AR47. Code Breakpoint May Be Taken after POP SS Instruction If It Is followed by an Instruction That Faults Probl

Errata 38 Specification Update AR49. IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly Problem: The IO_SMI bit in SMRAM's

Errata Specification Update 39 AR51. Using Memory Type Aliasing with Memory Types WB/WT May Lead to Unpredictable Behavior Problem: Memory type

4 Specification Update Revision History Revision Description Date -001 Initial release June 2007 -002 Added Note in Component Marking s

Errata 40 Specification Update AR54. MOV To/From Debug Registers Causes Debug Exception Problem: When in V86 mode, if a MOV instruction is exe

Errata Specification Update 41 AR55. EFLAGS Discrepancy on a Page Fault after a Multiprocessor TLB Shootdown Problem: This erratum may occur wh

Errata 42 Specification Update AR56. LBR, BTS, BTM May Report a Wrong Address When an Exception/Interrupt Occurs in 64-bit Mode Problem: An ex

Errata Specification Update 43 AR59. Returning to Real Mode from SMM with EFLAGS.VM Set May Result in Unpredictable System Behavior Problem: Re

Errata 44 Specification Update AR62. CPL-Qualified BTS May Report Incorrect Branch-From Instruction Address Problem: CPL (Current Privilege Le

Errata Specification Update 45 AR65. PEBS Buffer Overflow Status Will Not Be Indicated Unless IA32_DEBUGCTL[12] is Set Problem: IA32_PERF_GLOBA

Errata 46 Specification Update AR68. B0-B3 Bits in DR6 May Not Be Properly Cleared after Code Breakpoint Problem: B0-B3 bits (breakpoint condi

Errata Specification Update 47 AR71. Performance Monitor SSE Retired Instructions May Return Incorrect Values Problem: The SIMD_INST_RETIRED (E

Errata 48 Specification Update AR74. A MOV Instruction from CR8 Register with 16 Bit Operand Size Will Leave Bits 63:16 of the Destination Regi

Errata Specification Update 49 AR77. Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame Problem: The ENTER instruction i

Preface Specification Update 5 Preface This document is an update to the specifications contained in the documents listed in the following Affect

Errata 50 Specification Update AR80. Page Access Bit May Be Set Prior to Signaling a Code Segment Limit Fault Problem: If code segment limit i

Errata Specification Update 51 AR83. EFLAGS, CR0, CR4 and the EXF4 Signal May Be Incorrect after Shutdown Problem: When the processor is going

Errata 52 Specification Update AR86. Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is Counted Incorrectly for PMULUDQ Instruction Proble

Errata Specification Update 53 AR88. Updating Code Page Directory Attributes without TLB Invalidation May Result in Improper Handling of Code #

Errata 54 Specification Update AR90. Store Ordering May Be Incorrect between WC and WP Memory Types Problem: According to Intel® 64 and IA-32

Errata Specification Update 55 AR93. A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware Problem:

Errata 56 Specification Update AR96. PMI While LBR Freeze Enabled May Result in Old/Out-of-Date LBR Information Problem: When Precise Event-Ba

Errata Specification Update 57 AR99. Instruction Fetch May Cause a Livelock during Snoops of the L1 Data Cache Problem: A livelock may be obser

Errata 58 Specification Update AR101. A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to Memory-Ordering Violations Problem: Under cer

Errata Specification Update 59 AR103 RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execu

Preface 6 Specification Update Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their u

Errata 60 Specification Update AR105 Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown Problem: According to the Int

Specification Changes Specification Update 61 Specification Changes There are no specification changes for this specification update revision.

Specification Clarifications 62 Specification Update Specification Clarifications AR1 Clarification of Translation Lookaside Buffers (TLBS) Inv

Documentation Changes Specification Update 63 Documentation Changes There are no documentation changes for this specification update revision.

Identification Information Specification Update 7 Identification Information Component Identification via Programming Interface The Intel® Celero

Identification Information 8 Specification Update Component Marking Information Figure 1. Intel® Celeron® Processor 500 Series (Micro-FCPGA) Mar

Summary Tables of Changes Specification Update 9 Summary Tables of Changes The following table indicates the Specification Changes, Errata, Speci