Intel NE80546RE083256 Datenblatt

Document Number: 311826-005Intel® Celeron® D Processor 300Δ SequenceDatasheet– On 65 nm Process in the 775-Land Package March 2007

Introduction10 Datasheet1.1.1 Processor Packaging TerminologyCommonly used terms are explained here for clarification:• Intel® Celeron® D Processor 30

Datasheet 11Introduction1.2 ReferencesMaterial and concepts available in the following documents may be beneficial when reading this document.§ §Table

Introduction12 Datasheet

Datasheet 13Electrical Specifications2 Electrical SpecificationsThis chapter describes the electrical characteristics of the processor interfaces and

Electrical Specifications14 Datasheet2.2.2 VTT DecouplingDecoupling must be provided on the motherboard. Decoupling solutions must be sized to meet th

Datasheet 15Electrical SpecificationsTable 2. Voltage Identification DefinitionVID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID0 0

Electrical Specifications16 Datasheet2.4 Reserved, Unused, and TESTHI SignalsAll RESERVED lands must remain unconnected. Connection of these lands to

Datasheet 17Electrical Specifications2.5 Voltage and Current Specification2.5.1 Absolute Maximum and Minimum RatingsTable 3 specifies absolute maximum

Electrical Specifications18 Datasheet2.5.2 DC Voltage and Current SpecificationTable 4. Voltage and Current SpecificationsSymbol Parameter Min Typ Max

Datasheet 19Electrical SpecificationsNOTES:1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empir

2 DatasheetINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO AN

Electrical Specifications20 Datasheet Table 5. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A and 775_VR_CONFIG_06 ProcessorsICC (A)Voltage

Datasheet 21Electrical SpecificationsNOTES:1. The loadline specification includes both static and transient limits except for overshoot allowed as sho

Electrical Specifications22 DatasheetNOTES:1. VOS is measured overshoot voltage.2. TOS is measured time duration above VID.2.5.4 Die Voltage Validatio

Datasheet 23Electrical Specifications2.6.1 FSB Signal GroupsThe front side bus signals have been combined into groups by buffer type. GTL+ input signa

Electrical Specifications24 DatasheetNOTES:1. Refer to Section 4.2 for signal descriptions.2. The value of these signals during the active-to-inactive

Datasheet 25Electrical Specifications2.6.2 GTL+ Asynchronous SignalsLegacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS inpu

Electrical Specifications26 Datasheet.Table 11. GTL+ Asynchronous Signal Group DC SpecificationsSymbol Parameter Min Max Unit Notes1NOTES:1. Unless ot

Datasheet 27Electrical Specifications5. 0.24 V is defined at 20% of nominal VTT of 1.2 V.6. The TAP signal group must meet the signal quality specific

Electrical Specifications28 Datasheet2.6.3.1 GTL+ Front Side Bus SpecificationsIn most cases, termination resistors are not required as these are inte

Datasheet 29Electrical Specifications2.7 Clock Specifications2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor ClockingBCLK[1:0] directly controls

Datasheet 3Contents1 Introduction...91.1

Electrical Specifications30 Datasheet2.7.2 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the proc

Datasheet 31Electrical Specifications.NOTES:1. Diagram not to scale.2. No specification for frequencies beyond fcore (core frequency).3. fpeak, if exi

Electrical Specifications32 Datasheet2.7.4 BCLK[1:0] Specifications§ §Table 19. Front Side Bus Differential BCLK SpecificationsSymbol Parameter Min Ty

Datasheet 33Package Mechanical Specifications3 Package Mechanical SpecificationsThe Celeron D processor is packaged in a Flip-Chip Land Grid Array (FC

Package Mechanical Specifications34 DatasheetFigure 5. Processor Package Drawing (Sheet 1 of 3)

Datasheet 35Package Mechanical SpecificationsFigure 6. Processor Package Drawing (Sheet 2 of 3)

Package Mechanical Specifications36 DatasheetFigure 7. Processor Package Drawing (Sheet 3 of 3)

Datasheet 37Package Mechanical Specifications3.2 Processor Component Keep-Out ZonesThe processor may contain components on the substrate that define c

Package Mechanical Specifications38 Datasheet3.5 Package Insertion SpecificationsThe Celeron D processor can be inserted into and removed from a LGA77

Datasheet 39Package Mechanical Specifications3.9 Processor Land CoordinatesFigure 9 shows the top view of the processor land coordinates. The coordina

4 Datasheet5.2.5 TCONTROL and Fan Speed Reduction ...815.2.6 Thermal Diode...

Package Mechanical Specifications40 Datasheet

Datasheet 41Land Listing and Signal Descriptions4 Land Listing and Signal DescriptionsThis chapter provides the processor land assignment and signal d

Land Listing and Signal Descriptions42 DatasheetFigure 10.land-out Diagram (Top View – Left Side)30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15ANVCC

Datasheet 43Land Listing and Signal DescriptionsFigure 11.land-out Diagram (Top View – Right Side)14 13 12 11 10 9 8 7 6 5 4 3 2 1VCC VSS VCC VCC VSS

Land Listing and Signal Descriptions44 DatasheetTable 23.Alphabetical Land AssignmentsLand NameLand #Signal Buffer TypeDirectionA3# L5 Source Synch In

Land Listing and Signal DescriptionsDatasheet 45D19# E9 Source Synch Input/OutputD20# D7 Source Synch Input/OutputD21# E10 Source Synch Input/OutputD2

Land Listing and Signal Descriptions46 DatasheetHIT# D4 Common Clock Input/OutputHITM# E4 Common Clock Input/OutputIERR# AB2 Asynch GTL+ OutputIGNNE#

Land Listing and Signal DescriptionsDatasheet 47TRST# AG1 TAP InputVCC AA8 Power/Other VCC AB8 Power/Other VCC AC23 Power/Other VCC AC24 Power/Othe

Land Listing and Signal Descriptions48 DatasheetVCC AJ19 Power/Other VCC AJ21 Power/Other VCC AJ22 Power/Other VCC AJ25 Power/Other VCC AJ26 Power

Land Listing and Signal DescriptionsDatasheet 49VCC J29 Power/Other VCC J30 Power/Other VCC J8 Power/Other VCC J9 Power/Other VCC K23 Power/Other

Datasheet 5Figures1VCC Static and Transient Tolerance for 775_VR_CONFIG_05A and 775_VR_CONFIG_06 Processors ...

Land Listing and Signal Descriptions50 DatasheetVID3 AL6 Power/Other OutputVID4 AK4 Power/Other OutputVID5 AL4 Power/Other OutputVSS B1 Power/Other V

Land Listing and Signal DescriptionsDatasheet 51VSS AG16 Power/Other VSS AG17 Power/Other VSS AG20 Power/Other VSS AG23 Power/Other VSS AG24 Power

Land Listing and Signal Descriptions52 DatasheetVSS C13 Power/Other VSS C16 Power/Other VSS C19 Power/Other VSS C22 Power/Other VSS C24 Power/Othe

Land Listing and Signal DescriptionsDatasheet 53VSS P23 Power/Other VSS P24 Power/Other VSS P25 Power/Other VSS P26 Power/Other VSS P27 Power/Othe

Land Listing and Signal Descriptions54 DatasheetTable 24.Numerical Land AssignmentLand #Land NameSignal Buffer TypeDirectionA2 VSS Power/Other A3 RS2

Land Listing and Signal DescriptionsDatasheet 55C22 VSS Power/Other C23 VCCIOPLL Power/Other C24 VSS Power/Other C25 VTT Power/Other C26 VTT Power

Land Listing and Signal Descriptions56 DatasheetF15 D30# Source Synch Input/OutputF16 VSS Power/Other F17 D37# Source Synch Input/OutputF18 D38# Sour

Land Listing and Signal DescriptionsDatasheet 57J6 REQ4# Source Synch Input/OutputJ7 VSS Power/Other J8 VCC Power/Other J9 VCC Power/Other J10 VCC

Land Listing and Signal Descriptions58 DatasheetN8 VCC Power/Other N23 VCC Power/Other N24 VCC Power/Other N25 VCC Power/Other N26 VCC Power/Other

Land Listing and Signal DescriptionsDatasheet 59V8 VCC Power/Other V23 VSS Power/Other V24 VSS Power/Other V25 VSS Power/Other V26 VSS Power/Other

6 DatasheetTables1 References ...112 Voltag

Land Listing and Signal Descriptions60 DatasheetAC7 VSS Power/Other AC8 VCC Power/Other AC23 VCC Power/Other AC24 VCC Power/Other AC25 VCC Power/O

Land Listing and Signal DescriptionsDatasheet 61AF25 VSS Power/Other AF26 VSS Power/Other AF27 VSS Power/Other AF28 VSS Power/Other AF29 VSS Power

Land Listing and Signal Descriptions62 DatasheetAJ15 VCC Power/Other AJ16 VSS Power/Other AJ17 VSS Power/Other AJ18 VCC Power/Other AJ19 VCC Power

Land Listing and Signal DescriptionsDatasheet 63AM5 FC11 Power/Other OutputAM6 VTTPWRGD Power/Other InputAM7 FC12 Power/Other OutputAM8 VCC Power/Oth

Land Listing and Signal Descriptions64 Datasheet4.2 Alphabetical Signals ReferenceTable 25. Signal Description (Sheet 1 of 9)Name Type DescriptionA[35

Datasheet 65Land Listing and Signal DescriptionsBCLK[1:0] InputThe differential pair BCLK (Bus Clock) determines the FSB frequency. All processor FSB

Land Listing and Signal Descriptions66 DatasheetBSEL[2:0] OutputThe BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor inpu

Datasheet 67Land Listing and Signal DescriptionsDBR# OutputDBR# (Debug Reset) is used only in processor systems where no debug port is implemented on

Land Listing and Signal Descriptions68 DatasheetFERR#/PBE# OutputFERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its

Datasheet 69Land Listing and Signal DescriptionsINIT# InputINIT# (Initialization), when asserted, resets integer registers inside the processor withou

Datasheet 7Revision HistoryRev No. Description Date-001 • Initial release May 2006-002• Added 775_VR_CONFIG_06 Specifications• Added Celeron D process

Land Listing and Signal Descriptions70 DatasheetMSID[1:0] InputMSID0 is used to indicate to the processor whether the platform supports 775_VR_CONFIG_

Datasheet 71Land Listing and Signal DescriptionsRSP# InputRSP# (Response Parity) is driven by the response agent (the agent responsible for completion

Land Listing and Signal Descriptions72 DatasheetTHERMTRIP# OutputIn the event of a catastrophic cooling failure, the processor will automatically shut

Datasheet 73Land Listing and Signal Descriptions§ §VSS_MB_REGULATIONOutputThis land is provided as a voltage regulator feedback sense point for VSS. I

Land Listing and Signal Descriptions74 Datasheet

Datasheet 75Thermal Specifications and Design Considerations5 Thermal Specifications and Design Considerations5.1 Processor Thermal SpecificationsThe

Thermal Specifications and Design Considerations76 DatasheetThe case temperature is defined at the geometric top center of the processor. Analysis ind

Datasheet 77Thermal Specifications and Design ConsiderationsTable 28. Thermal Profile for 775_VR_CONFIG_05A Processors Power (W)Maximum Tc (°C)Power (

Thermal Specifications and Design Considerations78 DatasheetTable 29. Thermal Profile for 775_VR_CONFIG_06 ProcessorsPower (W)Maximum Tc (°C)Power (W)

Datasheet 79Thermal Specifications and Design Considerations5.1.2 Thermal MetrologyThe maximum and minimum case temperatures (TC) for the Celeron D pr

8 DatasheetIntel® Celeron® D Processor 300 Sequence FeaturesThe Intel® Celeron® D processor family expands Intel’s processor family into the value-pri

Thermal Specifications and Design Considerations80 Datasheetperiods of TCC activation is expected to be so minor that it would be immeasurable. An und

Datasheet 81Thermal Specifications and Design Considerations5.2.3 PROCHOT# SignalAn external signal, PROCHOT# (processor hot), is asserted when the pr

Thermal Specifications and Design Considerations82 Datasheettemperature. Transistor Model parameters (Table 31) have been added to support thermal sen

Datasheet 83Thermal Specifications and Design ConsiderationsWhen calculating a temperature based on thermal diode measurements, a number of parameters

Thermal Specifications and Design Considerations84 Datasheet

Datasheet 85Features6 Features6.1 Power-On Configuration OptionsSeveral configuration options can be configured by hardware. The Celeron D processor s

Features86 Datasheet6.2.1 Normal StateThis is the normal operating state for the processor.6.2.2 HALT and Enhanced HALT Powerdown StatesThe Celeron D

Datasheet 87Features6.2.2.1 HALT Powerdown StateHALT is a low power state entered when all the logical processors have executed the HALT or MWAIT inst

Features88 DatasheetWhile in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the proc

Datasheet 89Boxed Processor Specifications7 Boxed Processor SpecificationsThe Celeron D processor will also be offered as an Intel boxed processor. In

Datasheet 9Introduction1 IntroductionThe Intel® Celeron® D processors 365, 360, 356, 352, and 347 are single-core desktop processors on the 65 nm proc

Boxed Processor Specifications90 DatasheetClearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The physical s

Datasheet 91Boxed Processor Specifications7.1.2 Boxed Processor Fan Heatsink WeightThe boxed processor fan heatsink will not weigh more than 550 grams

Boxed Processor Specifications92 DatasheetNote: The boxed processor’s fan heatsink requires a constant +12 V supplied to pin 2 and does not support va

Datasheet 93Boxed Processor Specifications7.3 Thermal SpecificationsThis section describes the cooling requirements of the fan heatsink solution utili

Boxed Processor Specifications94 Datasheet § §Figure 22. Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Side 1 View)Figure 23. Boxed Pro

Datasheet 95Debug Tools Specifications8 Debug Tools Specifications8.1 Logic Analyzer Interface (LAI)Intel is working with two logic analyzer vendors t