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Datasheet, Volume 2 205

Processor Configuration Registers

2.11.3 PVCCTL—Port VC Control Register

2.11.4 VC0RCAP—VC0 Resource Capability Register

B/D/F/Type: 0/6/0/MMR

Address Offset: 10C–10Dh

Reset Value: 0000h

Access: RW, RO

Size: 16 bits

BIOS Optimal Default 000h

Bit Access

Reset

Value

RST/

PWR

Description

15:4 RO 0h Reserved (RSVD)

3:1 RW 000b Uncore

VC Arbitration Select (VCAS)

This field will be programmed by software to the only possible

value as indicated in the VC Arbitration Capability field. Since

there is no other VC supported than the default, this field is

reserved.

0RO 0bUncore

Reserved for Load VC Arbitration Table (VCARB)

Used for software to update the VC Arbitration Table when VC

arbitration uses the VC Arbitration Table. As a VC Arbitration

Table is never used by this component this field will never be

used.

B/D/F/Type: 0/6/0/MMR

Address Offset: 110–113h

Reset Value: 00000001h

Access: RO

Size: 32 bits

BIOS Optimal Default 00h

Bit Access

Reset

Value

RST/

PWR

Description

31:24 RO 00h Uncore Reserved for Port Arbitration Table Offset (PATO)

23 RO 0h Reserved (RSVD)

22:16 RO 00h Uncore Reserved for Maximum Time Slots (MTS)

15 RO 0b Uncore

Reject Snoop Transactions (RSNPT)

0 = Transactions with or without the No Snoop bit set within the

TLP header are allowed on this VC.

1 = When set, any transaction for which the No Snoop attribute

is applicable but is not set within the TLP Header will be

rejected as an Unsupported Request

14:8 RO 0h Reserved (RSVD)

1 2 ... 200 201 202 203 204 205 206 207 208 209 210 ... 341 342

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