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Document Number: 327405-001
Intel
®
Xeon
®
and Intel
®
Core™
Processors For Communications
Infrastructure
Datasheet - Volume 1 of 2
Supporting:
Intel
®
Xeon
®
Processor E3-1125C
Intel
®
Xeon
®
Processor E3-1105C
Intel
®
Core™ i3 Processor 2115C
Intel
®
Pentium
®
Processor B915C
Intel
®
Celeron
®
Processor 725C
Document #324803 - 2nd Generation Intel
®
Core™ Processor Family Mobile Datasheet -
Volume 2 completes the documentation set and contains additional product information.
May 2012
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1 2 3 4 5 6 ... 163 164

Inhaltsverzeichnis

Seite 1 - May 2012

Document Number: 327405-001Intel® Xeon® and Intel® Core™ Processors For Communications InfrastructureDatasheet - Volume 1 of 2Supporting: Intel® Xeo

Seite 2 - Legal Lines and Disclaimers

ContentsIntel® Xeon® and Intel® Core™ Processors For Communications InfrastructureDatasheet - Volume 1 of 2 May 201210 Document Number: 327405-001

Seite 3 - Revision History

Electrical SpecificationsIntel® Xeon® and Intel® Core™ Processors For Communications InfrastructureDatasheet - Volume 1 of 2 May 2012100 Document Numb

Seite 4 - Contents

Electrical SpecificationsIntel® Xeon® and Intel® Core™ Processors For Communications InfrastructureMay 2012 Datasheet - Volume 1 of 2Document Number:

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Electrical SpecificationsIntel® Xeon® and Intel® Core™ Processors For Communications InfrastructureMay 2012 Datasheet - Volume 1 of 2Document Number:

Seite 11 - 1.0 Introduction

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Electrical SpecificationsIntel® Xeon® and Intel® Core™ Processors For Communications InfrastructureMay 2012 Datasheet - Volume 1 of 2Document Number:

Seite 13 - 1.3 Terminology

IntroductionIntel® Xeon® and Intel® Core™ Processors For Communications InfrastructureMay 2012 Datasheet 1 of 2Document Number: 327405-001 111.0 Intro

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Electrical SpecificationsIntel® Xeon® and Intel® Core™ Processors For Communications InfrastructureDatasheet - Volume 1 of 2 May 2012110 Document Numb

Seite 15 - 2.0 Product Overview

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Seite 16 - Processor

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Seite 17 - 2.4 Interface Features

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Seite 18 - 2.4.2 PCI Express*

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Seite 21 - 2.8 Testability

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Seite 23 - 3.0 Interfaces

Processor Ball and Package InformationIntel® Xeon® and Intel® Core™ Processors For Communications InfrastructureMay 2012 Datasheet - Volume 1 of 2Docu

Seite 24 - 3.1.1.1 UDIMM Configurations

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Seite 27 - Flex Memory Technology Mode

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Seite 28 - Fast Memory Access

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Seite 29 - 3.1.5.2 Command Overlap

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Seite 31 - 3.2.1.3 Physical Layer

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Seite 35 - 3.2.5 Configuring PCIe* Lanes

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Seite 36 - 3.3 Direct Media Interface

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Seite 37 - 3.5 Interface Clocking

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Seite 39 - 4.0 Technologies

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Seite 40 - VT-d Features

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Seite 41 - 4.3 Intel

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Seite 42 - 4.4.1 PCLMULQDQ Instruction

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Seite 45 - 5.0 Processor SKUs

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Seite 47 - 6.0 Power Management

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Seite 48 - 6.1 ACPI States Supported

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Seite 49 - 6.1.5 DMI States

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Seite 50 - Core 0 State

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Seite 51 - C1 C1E C7C6C3

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Seite 52 - 6.2.4.2 Core C1/C1E State

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Seite 53 - 6.2.4.6 C-State Auto-Demotion

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Seite 55 - 6.2.5.2 Package C1/C1E

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Seite 56 - 6.2.5.5 Package C7 State

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Seite 57 - 6.3 IMC Power Management

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Seite 59 - 6.4 PCIe* Power Management

Processor Configuration RegistersIntel® Xeon® and Intel® Core™ Processors For Communications InfrastructureMay 2012 Datasheet - Volume 1 of 2Document

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Seite 61 - 7.0 Thermal Management

Processor Configuration RegistersIntel® Xeon® and Intel® Core™ Processors For Communications InfrastructureMay 2012 Datasheet - Volume 1 of 2Document

Seite 62 - Table 7-1. TDP Specifications

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Seite 78 - 8.9 Power Sequencing

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Seite 79 - 8.12 Future Compatibility

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Seite 81 - 9.0 Electrical Specifications

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Seite 82 - 9.3.1 PLL Power Supply

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Seite 110 - Cl ock-Cl ock#

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Seite 111 - Programmable

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Seite 115 - Overshoot Specification

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Seite 116 - Voltage (V)

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