Intel BX80525KY500512 Datenblatt

Pentium® III Xeon™ Processor at 500 and 550 MHz DatasheetProduct FeaturesThe Intel® Pentium® III Xeon™ processor is designed for mid-range to high-en

Pentium® III Xeon™ Processor at 500 and 550 MHz10DatasheetThe term “Pentium III Xeon processor” refers to the cartridge package which interfaces to a

Pentium® III Xeon™ Processor at 500 and 550 MHz100DatasheetTable 50. I/O Signals (Single Driver) Name Active Level Cloc Signal Group QualifiedA[35:03

Datasheet101Pentium® III Xeon™ Processor at 500 and 550 MHz1.0 Introduction...

Pentium® III Xeon™ Processor at 500 and 550 MHz102 Datasheet4.3.6.1 Thermal Reference Registers...46

Datasheet103Pentium® III Xeon™ Processor at 500 and 550 MHz9.1.2 A20M# (I)...

Pentium® III Xeon™ Processor at 500 and 550 MHz104 Datasheet9.1.52 STPCLK# (I) ...

Datasheet105Pentium® III Xeon™ Processor at 500 and 550 MHz1 Timing Diagram of Clock Ratio Signals ...

Pentium® III Xeon™ Processor at 500 and 550 MHz106 Datasheet

Datasheet107Pentium® III Xeon™ Processor at 500 and 550 MHz1 Core Frequency to System Bus Multiplier Configuration...

Pentium® III Xeon™ Processor at 500 and 550 MHz108 Datasheet51 I/O Signals (Multiple Driver)...

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet11•Pentium® II Xeon™ Processor Support Component Vendor List (http://developer.intel.com/desi

UNITED STATES, Intel Corporation2200 Mission College Blvd., P.O. Box 58119, Santa Clara, CA 95052-8119Tel: +1 408 765-8080JAPAN, Intel Japan K.K.5-6

Pentium® III Xeon™ Processor at 500 and 550 MHz12Datasheetprovide termination for each Pentium III Xeon processor. These specifications assume the equ

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet13when the part is powering on, or entering/exiting low power states, is provided on the volt

Pentium® III Xeon™ Processor at 500 and 550 MHz14DatasheetSee Figure 1 for the timing relationship between the system bus multiplier signals, RESET#,

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet15Note:Signal Integrity issues may require this circuit to be modified.2.4.1 Mixing Processor

Pentium® III Xeon™ Processor at 500 and 550 MHz16Datasheet2.5 Voltage IdentificationThe Pentium III Xeon processor contains five voltage identificatio

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet17NOTES1. 0 = Processor pin connected to VSS, 1 = Open on processor; may be pulled up to TTL

Pentium® III Xeon™ Processor at 500 and 550 MHz18DatasheetWhen tying any signal to power or ground, a resistor will also allow for system testability.

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet19NOTES1. The BR0# pin is the only BREQ# signal that is bi-directional. The internal BREQ# si

DatasheetInformation in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any

Pentium® III Xeon™ Processor at 500 and 550 MHz20Datasheet2.9 Maximum RatingTable 4 contains Pentium III Xeon processor stress ratings. Functional ope

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet21Most of the signals on the Pentium III Xeon processor system bus are in the AGTL+ signal gr

Pentium® III Xeon™ Processor at 500 and 550 MHz22Datasheetconnector is specified to have a pin self-inductance of 6.0 nH maximum, a pin-to-pin capacit

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet23negative current flow due to the active pull-up to VCCCORE in the Pentium III Xeon processo

Pentium® III Xeon™ Processor at 500 and 550 MHz24DatasheetNOTES:1. (0 ≤ VIN ≤ 2.62 5V).2. (0 ≤ VOUT ≤ 2.62 5V).† SMBALERT# is an open drain signal.2.1

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet25NOTES1. The Pentium® III Xeon™ processor contains 1% AGTL+ termination resistors at the end

Pentium® III Xeon™ Processor at 500 and 550 MHz26Datasheetallowed between adjacent cycles. Positive or negative jitter of up to 250 ps is tolerated, b

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet27BCLK has met the BCLK AC specifications in Table 11 for at least 10 clock cycles. PWRGOOD m

Pentium® III Xeon™ Processor at 500 and 550 MHz28DatasheetNOTES:1. Unless otherwise noted, these specifications are tested during manufacturing.2. Not

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet29Figure 4 through Figure 12 are to be used in conjunction with the DC specification and AC t

Datasheet3Pentium® III Xeon™ Processor at 500 and 550 MHzContents1.0 Introduction...

Pentium® III Xeon™ Processor at 500 and 550 MHz30DatasheetFigure 7. Setup and Hold TimingsFigure 8. FRC Mode BCLK to PICCLK TimingClockSignalVValidT

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet31Figure 9. System Bus Reset and Configuration TimingsFigure 10. Power-On Reset and Configur

Pentium® III Xeon™ Processor at 500 and 550 MHz32Datasheet3.0 Signal QualitySignals driven on the Pentium III Xeon processor system bus should meet si

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet333.1 System Bus Clock Signal Quality SpecificationsTable 18 describes the signal quality spe

Pentium® III Xeon™ Processor at 500 and 550 MHz34Datasheet3.2.1 AGTL+ Ringback Tolerance SpecificationsTable 19 provides the AGTL+ signal quality spec

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet353.3 Non-AGTL+ Signal Quality SpecificationsThere are three signal quality parameters define

Pentium® III Xeon™ Processor at 500 and 550 MHz36Datasheet3.3.3 2.5 V Tolerant Buffer Settling Limit GuidelineSettling limit defines the maximum amoun

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet374.2 Low Power States and Clock ControlThe Pentium III Xeon processor allows the use of Auto

Pentium® III Xeon™ Processor at 500 and 550 MHz38Datasheet4.2.3 Stop-Grant State — State 3The Stop-Grant state on the Pentium III Xeon processor is en

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet394.2.4 Halt/Grant Snoop State — State 4The Pentium III Xeon processor will respond to snoop

Pentium® III Xeon™ Processor at 500 and 550 MHz4 Datasheet4.3.3 Processor Information ROM and Scratch EEPROM Supported SMBus Transactions ...

Pentium® III Xeon™ Processor at 500 and 550 MHz40DatasheetThe processor will not enter any low power states until all internal queues for the second l

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet414.3.1 Processor Information ROMAn electrically programmed read-only memory with information

Pentium® III Xeon™ Processor at 500 and 550 MHz42Datasheet4.3.2 Scratch EEPROMAlso available on the SMBus is an EEPROM which may be used for other dat

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet434.3.3 Processor Information ROM and Scratch EEPROM Supported SMBus TransactionsThe Processo

Pentium® III Xeon™ Processor at 500 and 550 MHz44Datasheetthermal diode is sensed and the precision A/D converter derives a single byte of thermal ref

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet45† This is an 8-bit field. The device which sent the alert will respond to the ARA Packet wi

Pentium® III Xeon™ Processor at 500 and 550 MHz46DatasheetAll of the commands are for reading or writing registers in the thermal sensor except the on

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet474.3.6.4 Configuration RegisterThe configuration register controls the operating mode (stand

Pentium® III Xeon™ Processor at 500 and 550 MHz48Datasheet4.3.7 SMBus Device AddressingOf the addresses broadcast across the SMBus, the memory compone

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet49NOTES1. Upper address bits are decoded in conjunction with the select pins.2. A tri-state o

Datasheet5Pentium® III Xeon™ Processor at 500 and 550 MHz8.2 Integration Tool (Logic Analyzer) Considerations ...

Pentium® III Xeon™ Processor at 500 and 550 MHz50Datasheet5.1 Thermal SpecificationsThis section provides power dissipation specifications for each va

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet51NOTES1. These values are specified at nominal VCCCORE for the processor core and nominal VC

Pentium® III Xeon™ Processor at 500 and 550 MHz52Datasheet5.2 Processor Thermal Analysis5.2.1 Thermal Solution PerformanceProcessor cooling solutions

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet53NOTES6. Interface agent suggestions: ShinEtsu* G749 or Thermoset* TC330; Dispense volume ad

Pentium® III Xeon™ Processor at 500 and 550 MHz54Datasheet2-Mbyte L2 cache products. Figure 20 shows the locations for TPLATE measurement directly abo

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet55areas on the cover have been characterized and are illustrated in Figure 23. If no external

Pentium® III Xeon™ Processor at 500 and 550 MHz56DatasheetTable 40 and Table 41 provide the edge finger and SC330 connector signal definitions for Pen

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet57Figure 25. S.E.C. Cartridge Cooling Solution Attach Details (Notes follow Figure 27)3.000 ±

Pentium® III Xeon™ Processor at 500 and 550 MHz58DatasheetFigure 26. S.E.C. Cartridge Retention Enabling Details (Notes follow Figure 27)6.000+.015- .

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet59NOTES1. Maximum protrusion of the mechanical heatsink attach media into cartridge during as

Pentium® III Xeon™ Processor at 500 and 550 MHz6 Datasheet9.1.47 SLP# (I) ...

Pentium® III Xeon™ Processor at 500 and 550 MHz60Datasheet6.1 WeightThe maximum weight of a Pentium III Xeon processor is approximately 500 grams.6.2

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet61NOTE:5. Retention devices for this cartridge must accommodate this cartridge “Float” relati

Pentium® III Xeon™ Processor at 500 and 550 MHz62Datasheet6.3 Pentium® III Xeon™ Processor Substrate Edge Finger Signal ListingTable 40 is the Pentium

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet63A38 DEP#[1] AGTL+ I/O B38 VCC_CORE CPU Core VCCA39 DEP#[3] AGTL+ I/O B39 DEP#[2] AGTL+ I/OA

Pentium® III Xeon™ Processor at 500 and 550 MHz64DatasheetA81 VSS Ground B81 D#[20] AGTL+ I/OA82 TEST_VTT_A82 Pull up to VTTB82 VCC_CORE CPU Core VCCA

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet65A124 A#[04] AGTL+ I/O B124 A#[03] AGTL+ I/OA125 VSS Ground B125 A#[06] AGTL+ I/OA126 RESERV

Pentium® III Xeon™ Processor at 500 and 550 MHz66DatasheetTable 41. Signal Listing in Order by Pin Name (Sheet 1 of 9)Pin No. Pin Name Signal Buffer

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet67B74 D#[26] AGTL+ I/OA73 D#[27] AGTL+ I/OB71 D#[28] AGTL+ I/OB72 D#[29] AGTL+ I/OA71 D#[30]

Pentium® III Xeon™ Processor at 500 and 550 MHz68DatasheetA83 RESERVED_A83 DO NOT CONNECTB163 RESERVED_B163 DO NOT CONNECTB22 RESERVED_B22 DO NOT CONN

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet69B118 VCC_L2 L2 Cache VCCB120 VCC_L2 L2 Cache VCCB123 VCC_L2 L2 Cache VCCB126 VCC_L2 L2 Cach

Datasheet7Pentium® III Xeon™ Processor at 500 and 550 MHz29 Top View of Cartridge Insertion Pressure Points ...

Pentium® III Xeon™ Processor at 500 and 550 MHz70DatasheetA93 VSS GroundA96 VSS GroundA99 VSS GroundA156 VTT AGTL+ VTT SupplyA157 VTT AGTL+ VTT Supply

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet717.0 Boxed Processor Specifications7.1 IntroductionThe Pentium III Xeon processor is also of

Pentium® III Xeon™ Processor at 500 and 550 MHz72DatasheetFigure 32. Side View Space Requirements for the Boxed ProcessorAB

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet737.2.1Boxed Processor Heatsink Dimensions7.2.2Boxed Processor Heatsink WeightThe boxed proce

Pentium® III Xeon™ Processor at 500 and 550 MHz74Datasheetsystem integrators should include a retention mechanism and appropriate installation instruc

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet75Figure 34. Front Views of the Boxed Processor with Attached Auxiliary Fan (Not Included wit

Pentium® III Xeon™ Processor at 500 and 550 MHz76Datasheet7.3.2.1 Clearance Recommendations for Auxiliary FanIf an auxiliary fan is used, clearance mu

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet777.3.2.2 Fan Power Recommendations for Auxiliary FanTo facilitate power to the auxiliary fan

Pentium® III Xeon™ Processor at 500 and 550 MHz78Datasheet7.3.2.3 Thermal Evaluation for Auxiliary FanGiven the complex and unique nature of baseboard

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet79debug interface. Due to the nature of an ITP, the processor may be controlled without affec

Pentium® III Xeon™ Processor at 500 and 550 MHz8 Datasheet26 Byte Write SMBus Packet ...

Pentium® III Xeon™ Processor at 500 and 550 MHz80Datasheet8.1.3 Debug Port Signal DescriptionsTable 44 describes the debug port signals and provides t

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet81TDO 10 Test data output signal from last component in boundary scan chain of MP cluster to

Pentium® III Xeon™ Processor at 500 and 550 MHz82DatasheetNOTES:1. Resistor values with “~” preceding them can vary from the specified value; use resi

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet838.1.4.1 General Signal Quality NotesSignals from the debug port are fed to the system from

Pentium® III Xeon™ Processor at 500 and 550 MHz84DatasheetDue to the number of loads on the TCK signal, special care should be taken when routing this

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet85Note:The buffer rise and fall edge rates should NOT be FASTER than 3ns. Edge rates faster t

Pentium® III Xeon™ Processor at 500 and 550 MHz86Datasheet8.2 Integration Tool (Logic Analyzer) ConsiderationsTarget platforms must be designed to all

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet879.1.3 ADS# (I/O)The ADS# (Address Strobe) signal is asserted to indicate the validity of th

Pentium® III Xeon™ Processor at 500 and 550 MHz88Datasheet9.1.8 BINIT# (I/O)The BINIT# (Bus Initialization) signal may be observed and driven by all P

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet89Table 46 gives the interconnect between the processor and bus signals for a 2-way system.Du

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet91.0 IntroductionThe Pentium III Xeon processor is a follow-on to the Pentium Pro and Pentium

Pentium® III Xeon™ Processor at 500 and 550 MHz90Datasheet9.1.16 DBSY# (I/O)The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet91On the active-to-inactive transition of RESET#, each processor samples FLUSH# to determine

Pentium® III Xeon™ Processor at 500 and 550 MHz92DatasheetDuring active RESET#, the Pentium III Xeon processor begins sampling the A20M#, IGNNE# , and

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet939.1.31 L2_SENSEThe L2_SENSE pin is connected to the VCC_L2 power plane on the substrate.9.1

Pentium® III Xeon™ Processor at 500 and 550 MHz94DatasheetPWRGOOD can be driven inactive at any time, but clocks and power must again be stable before

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet959.1.42 RP# (I/O)The RP# (Request Parity) signal is driven by the request initiator, and pro

Pentium® III Xeon™ Processor at 500 and 550 MHz96Datasheetsignals to a Hi-Z state would cause ambiguity in the memory device address decode, possibly

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet979.1.52 STPCLK# (I)The STPCLK# (Stop Clock) signal, when asserted, causes processors to ente

Pentium® III Xeon™ Processor at 500 and 550 MHz98Datasheet9.1.59 TMS (I)The TMS (Test Mode Select) signal is a TAP support signal used by debug tools.

Pentium® III Xeon™ Processor at 500 and 550 MHz Datasheet99NOTES1. All asynchronous input signals except PWRGOOD must be synchronous in FRC.2. Synchro