Intel I5 Bedienungsanleitung

Reference Number: 326770Mobile 3rd Generation Intel® Core™ Processor Family Specification UpdateSeptember 2013Revision 015

10 Specification UpdateBU34XXNo FixProcessor May Fail to Acknowledge a TLP RequestBU35XXNo FixAn Unexpected PMI May Occur After Writing a Large Value

Specification Update 11BU63XXNo FixPCIe* Root-port Initiated Compliance State Transmitter Equalization Settings May be IncorrectBU64XXNo FixPCIe* Con

12 Specification UpdateBU94 X X No FixInstruction Fetches Page-Table Walks May be Made Speculatively to Uncacheable MemoryBU95 X X No Fix The Processo

Specification Update 13§ §

14 Specification UpdateIdentification InformationComponent Identification using Programming InterfaceThe processor stepping can be identified by the f

Specification Update 15Component Marking InformationThe processor stepping can be identified by the following component markings.Table 1. Processor I

16 Specification UpdateSR0MX i5-3320M L-1 000306A9h 2.6 / 1600 / 6504 core: 03 core: 02 core: 3.11 core: 3.33 2,3,4,5,6SR0MY i5-3320M L-1 000306A9h 2.

Specification Update 17SR0X7 i5-3380M L-1 000306A9h 2.9 /1600 /6502 core: 3.41 core: 3.63 2,3,4,5,6SR0X9 i5-3380M L-1 000306A9h 2.9 /1600 /6502 core:

18 Specification UpdateSR0ZN i5-3439Y L-1 000306A9h 1.5 /1600/ 3502 core: N/A1 core: 2.33 2,3,4,5,6SR12S i5-3339Y L-1 000306A9h 1.5 /1600/ 3502 core:

Specification Update 19SR0ND i7-3612QE E-1 00306A9h 2.3 / 1600/ 6503/4 Core: 2.82 Core: 3.01 Core: 3.16 2,3,4,5,6,8SR0T5 i7-3555LE L-1 00306A9h 2.5 /

2 Specification UpdateINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER

20 Specification UpdateNotes:1. This column indicates maximum Intel® Turbo Boost Technology 2.0 frequency (GHz) for 4,3, 2 or 1 cores active respectiv

Specification Update 21ErrataBU1. The Processor May Report a #TS Instead of a #GP FaultProblem: A jump to a busy TSS (Task-State Segment) may cause a

22 Specification UpdateBU4. Performance Monitor SSE Retired Instructions May Return Incorrect ValuesProblem: Performance Monitoring counter SIMD_INST_

Specification Update 23BU8. LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit ModeProblem: An exception/interrupt

24 Specification UpdateBU11. EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation ChangeProblem: This erratum is regardin

Specification Update 25BU13. MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB ErrorProblem: A single Data Translation Lo

26 Specification UpdateBU17. PEBS Record not Updated when in Probe ModeProblem: When a performance monitoring counter is configured for PEBS (Precise

Specification Update 27BU21. #GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error CodeProblem

28 Specification UpdateBU24. Changing the Memory Type for an In-Use Page Translation May Lead to Memory-Ordering ViolationsProblem: Under complex micr

Specification Update 29BU27. Fault Not Reported When Setting Reserved Bits of Intel® VT-d Queued Invalidation DescriptorsProblem: Reserved bits in th

ContentsSpecification Update 3ContentsRevision History...

30 Specification UpdateBU30. Spurious Interrupts May be Generated From the Intel® VT-d Remap EngineProblem: If software clears the F (Fault) bit 127 o

Specification Update 31BU34. Processor May Fail to Acknowledge a TLP RequestProblem: When a PCIe root port’s receiver is in Receiver L0s power state

32 Specification UpdateBU38. PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have OccurredProblem: Under very specific timing cond

Specification Update 33BU41. PCI Express* Differential Peak-Peak Tx Voltage Swing May Violate the SpecificationProblem: Under certain conditions, inc

34 Specification UpdateBU44. IA32_FEATURE_CONTROL MSR May be Uninitialized on a Cold ResetProblem: IA32_FEATURE_CONTROL MSR (3Ah) may have random valu

Specification Update 35BU48. 64-bit REP MOVSB/STOSB May Clear The Upper 32-bits of RCX, RDI And RSI Before Any Data is TransferredProblem: If a REP M

36 Specification UpdateBU52. Instructions Retired Event May Over Count Execution of IRET InstructionsProblem: Under certain conditions, the performanc

Specification Update 37BU56. PCI Express* Gen3 Receiver Return Loss May Exceed SpecificationsProblem: The PCIe Base Specification includes a graph th

38 Specification UpdateBU59. PCIe* May Associate Lanes That Are Not Part of Initial Link Training to L0 During UpconfigurationProblem: The processor s

Specification Update 39BU63. PCIe* Root-port Initiated Compliance State Transmitter Equalization Settings May be IncorrectProblem: If the processor i

Contents4 Specification Update

40 Specification UpdateBU67. MSR_PKG_Cx_RESIDENCY MSRs May Not be AccurateProblem: If the processor is in a package C-state for an extended period of

Specification Update 41BU72. PCIe* Root Port May Not Initiate Link Speed ChangeProblem: The PCIe Base specification requires the upstream component t

42 Specification UpdateBU75. VM Exits Due to “NMI-Window Exiting” May Not Occur Following a VM Entry to the Shutdown StateProblem: If VM entry is made

Specification Update 43BU78. PCIe* Controller May Not Enter LoopbackProblem: The PCIe controller is expected to enter loopback if any lane in the lin

44 Specification UpdateBU82. PCIe* Link May Fail Link Width UpconfigurationProblem: The processor supports PCIe Hardware Autonomous Width management,

Specification Update 45BU86. REP MOVSB May Incorrectly Update ECX, ESI, and EDIProblem: Under certain conditions, if the execution of a REP MOVSB ins

46 Specification UpdateBU89. VEX.L is Not Ignored with VCVT*2SI InstructionsProblem: The VEX.L bit should be ignored for the VCVTSS2SI, VCVTSD2SI, VCV

Specification Update 47BU93. During Package Power States Repeated PCIe* and/or DMI L1 Transitions May Cause a System HangProblem: Under a complex set

48 Specification UpdateBU97. VM Exits Due to GETSEC May Save an Incorrect Value for “Blocking by STI” in the Context of Probe-Mode RedirectionProblem:

Specification Update 49corresponding counter with the same number on the physical core’s other thread rather than the thread experiencing the event.

Specification Update 5Revision HistoryRevision Description Date001 • Initial Release. April 2012002• Added Errata BU69–BU85• Updated Processor Identi

50 Specification UpdateBU104. Processor May Livelock During On Demand Clock ModulationProblem: The processor may livelock when (1) a processor thread

Specification Update 51this field. (The processor correctly stores the guest-physical address of the paging-structure entry into the “guest-physical

52 Specification Updateprocessor micro-architectural events may cause an incorrect address translation or machine check on either logical processor.Im

Specification Update 53Specification ChangesThe Specification Changes listed in this section apply to the following documents:•Intel® 64 and IA-32 Ar

54 Specification UpdateSpecification ClarificationsThe Specification Clarifications listed in this section may apply to the following documents:•Intel

Specification Update 55Documentation ChangesThe Documentation Changes listed in this section apply to the following documents:•Intel® 64 and IA-32 Ar

56 Specification Update§ §DisplayFamily_DisplayModel DisplayFamily_DisplayModel DisplayFamily_DisplayModel DisplayFamily_DisplayModel 0F_xx 06_1C 06_1

6 Specification UpdatePrefaceThis document is an update to the specifications contained in the Affected Documents table below. This document is a comp

Specification Update 7NomenclatureErrata are design defects or errors. These may cause the processor behavior to deviate from published specification

8 Specification UpdateSummary Tables of ChangesThe following tables indicate the errata, specification changes, specification clarifications, or docum

Specification Update 9BU7XXNo FixGeneral Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted BU8XXNo FixLBR, BTS, BTM May