Intel SL22T Spezifikationen PDF herunterladen (Seite 10)

2-4

LOCAL X2APIC ARCHITECTURE

• The SELF IPI register is available only if x2APIC mode is enabled.

The MSR address space is compressed to allow for future growth. Every 32 bit

in the local x2APIC MSR address space. The upper 32-bits of all x2APIC MSRs (except

for the ICR) are reserved.

Table 2-2. Local APIC Register Address Map Supported by x2APIC

MMIO Offset

(xAPIC mode)

MSR Offset

(x2APIC

mode) Register Name

R/W

Semantics Comments

0000H-

0010H

000H-001H Reserved

0020H 002H Local APIC ID Register Read only See Section 2.7.1 for

initial values.

0030H 003H Local APIC Version

Read only. Same version between

extended and legacy

modes. Bit 24 is available

only to an x2APIC unit (in

xAPIC mode and x2APIC

modes, See Section 2.5.1).

0040H-

0070H

004H-007H Reserved

0080H 008H Task Priority Register

(TPR)

Read/Write. Bits 7:0 are RW. Bits 31:8

are Reserved.

0090H 009H Reserved

00A0H 00AH Processor Priority

Read only.

00B0H 00BH EOI Register Write only. 0 is the only valid value

to write. GP fault on non-

zero write

00C0H 00CH Reserved

00D0H 00DH Logical Destination

Read only. Read/Write in xAPIC

mode)

00E0H 00EH Reserved

GP fault on Read Write in

x2APIC mode.

00F0H 00FH Spurious Interrupt

Vector Register

Read/Write. Bits 0-8, 12 Read/Write;

other bits reserved.

0100H 010H In-Service Register

(ISR); bits 0:31

Read Only.

0110H 011H ISR bits 32:63 Read Only.

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 34 35

Kommentare zu diesen Handbüchern

Keine Kommentare

Intel SL22T Spezifikationen Seite 10

Kommentare zu diesen Handbüchern

Verwandte Produkte und Handbücher für Prozessoren Intel SL22T