Intel 8XC196NP Handbücher

Intel 8XC196NP Bedienungsanleitung (471 Seiten)

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Inhaltsverzeichnis

8XC196NP, 80C196NU

1

Microcontroller

1

User’s Manual

1

8XC196NP, 80C196NU

2

Microcontroller

2

User’s Manual

2

© INTEL CORPORATION, 1996

3

CONTENTS

4

Guide to This Manual

18

CHAPTER 1

20

GUIDE TO THIS MANUAL

20

8XC196NT Quick Reference

27

8XC196KR Quick Reference

27

8XC196KT Quick Reference

27

8XC196MC Quick Reference

27

8XC196NP Quick Reference

27

Page Intentionally Left Blank

28

Architectural

32

Overview

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CHAPTER 2

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ARCHITECTURAL OVERVIEW

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Clock and

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Power Mgmt

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2.3.3.1 Code Execution

37

2.3.3.2 Instruction Format

38

Generators

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A3160-01

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Advanced Math

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Features

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CHAPTER 3

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ADVANCED MATH FEATURES

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Programming

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CHAPTER 4

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PROGRAMMING CONSIDERATIONS

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• direct

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• immediate

63

be 24 bits to

67

Memory Partitions

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CHAPTER 5

74

A2541-02

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5.2 MEMORY PARTITIONS

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• FF2080–FF2FFFH

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Table 5-5. Peripheral SFRs

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CPU SFRs

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Page 00H

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5.2.4.2 Stack Pointer (SP)

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Table 5-7. CPU SFRs

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Figure 5-4. Windowing

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Table 5-10. Windows

90

A2513-03

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23 16 15 0

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MEMORY PARTITIONS

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Standard and PTS

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Interrupts

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CHAPTER 6

108

STANDARD AND PTS INTERRUPTS

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Reset INT_PEND

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Table 6-1. Interrupt Signals

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6.3.1.1 Unimplemented Opcode

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6.3.1.2 Software Trap

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6.3.1.3 NMI

113

6.4.2.2 PTS Interrupt Latency

116

Register

117

PWM Toggle

125

PWM Remap

125

6.6.2 Selecting the PTS Mode

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A2552-02

138

If EPA0, set the output

143

If EPA1, clear the output

143

I/O Ports

144

CHAPTER 7

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I/O PORTS

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Table 7-9. EPORT Pins

156

7.3.1 EPORT Operation

157

Figure 7-3. EPORT Structure

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7.3.1.5 Input Mode

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7.3.3.4 Design Considerations

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Serial I/O (SIO) Port

166

CHAPTER 8

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SERIAL I/O (SIO) PORT

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A0264-02

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Figure 8-3. Mode 0 Timing

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10-Bit Frame

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A0245-02

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11-Bit Frame

174

Programmable 9th Bit

174

Pulse-width

184

Modulator

184

CHAPTER 9

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PULSE-WIDTH MODULATOR

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9.2 PWM SIGNALS AND REGISTERS

187

9.3 PWM OPERATION

188

Figure 9-5. PWM Control (PWM

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_CONTROL) Register

193

A2390-02

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Event Processor

196

Array (EPA)

196

CHAPTER 10

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EVENT PROCESSOR ARRAY (EPA)

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EPA0 Interrupt

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EPA1 Interrupt

199

EPA2 Interrupt

199

EPA3 Interrupt

199

A0269-02

205

2 State

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10.4.1.1 EPA Overruns

208

• Clear EPAx_CON.0

209

_CON) Registers

216

_CON) Registers (Continued)

217

Minimum Hardware

226

Considerations

226

CHAPTER 11

228

XTAL1XTAL2

230

A3069-01

231

A0076-03

232

A0273-02

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+ 0.5 V

234

– 0.5 V

234

Internal

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values

236

8XC196 Device

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A0276-01

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Special Operating

240

CHAPTER 12

242

SPECIAL OPERATING MODES

242

Disable Clock Input

245

(Powerdown)

245

12.5.3.3 Selecting C

251

Interfacing with

256

External Memory

256

CHAPTER 13

258

7819 0111215 0111215

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R • • • R

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External Address ADDRCOM

263

) Register

267

• ADDRMSKx = XFFFH

268

• ADDRCOM1–ADDRCOM5 = X000H

268

Table 13-8. BUSCON

270

• Bus width (BW16): 8 bits

274

Bus Control

276

Address Bits 16–19

276

Address Bits 0–15

276

AD15:8 Address

277

256K×16

279

Data Address Data Address

280

Low Address

282

T0013-02

285

T0007-02

286

T0014-02

287

A2460-03

288

A2472-02

291

A0104-01

292

256K×8

293

A2367-05

294

T0011-02

295

A2368-05

296

T0012-02

297

T0010-02

298

Signals Conditions

299

Instruction Set

304

Reference

304

APPENDIX A

306

INSTRUCTION SET REFERENCE

306

Table A-5. Operand Variables

311

← (DEST) + (SRC)

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← (SRC1) + (SRC2)

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← (DEST) + (SRC) + C

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← (DEST) AND (SRC)

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← (SRC1) AND (SRC2)

313

← (DEST) –1

317

← (DEST) / (SRC)

318

← (DEST) MOD (SRC)

318

← (COUNT) –1

320

≠ 0 then

320

← PC + 8-bit disp

320

← SP – 4

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← PC + 24-bit disp

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←PC + 24-bit disp

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← (SRC) + 24-bit disp

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← (DEST) + 1

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← (DEST) × (SRC)

334

← (SRC1) × (SRC2)

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← – (DEST)

336

← (DEST) × 2

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← (COUNT) + 1

337

← NOT (DEST)

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← (DEST) OR (SRC)

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← SP + 2

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← (DEST) – (SRC)

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← (SRC1) – (SRC2)

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← (DEST) – (SRC) – (1–C)

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← (DEST X)

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← (DEST) XOR (SRC)

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Signal Descriptions

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APPENDIX B

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SIGNAL DESCRIPTIONS

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View of component as

377

B.2 SIGNAL DESCRIPTIONS

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Registers

390

APPENDIX C

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REGISTERS

392

Table C-3. ACC_0

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Addresses and Reset Values

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ACC_STAT

397

ADDRCOMx

399

ADDRMSKx

400

Table C-7. BUSCON

401

CON_REG0

404

EPA_MASK

409

EPA_PEND

410

EPAx_CON

411

EPAx_TIME

415

INT_MASK

416

INT_MASK1

417

INT_PEND

418

INT_PEND1

419

ONES_REG

420

Table C-10. P

421

Table C-11. P

422

Table C-13. P

423

Table C-14. P

424

PWMx_CONTROL

429

SP_STATUS

436

T1CONTROL

437

T2CONTROL

438

Table C-17. TIMER

439

ZERO_REG

446

Glossary

448

GLOSSARY

450

Glossary-2

451

Glossary-3

452

Glossary-4

453

Glossary-5

454

Glossary-6

455

Glossary-7

456

Glossary-8

457

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