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Intel
®
IXP42X Product Line of Network Proces
sors and IXC1100 Control Plane Processor
September 2006
DM
Order Number: 252480-006US
275
PCI Cont
roller—
Intel
®
IXP42X product line and
IXC1100 control plane proc
essors
1
2
...
270
271
272
273
274
275
276
277
278
279
280
...
567
568
IXP42X Product Line of
1
Control Plane Processor
1
DM September 2006
2
2 Order Number: 252480-006US
2
Contents
3
Revision History
23
1.0 Introduction
26
2.0 Overview of Product Line
30
Figure 1. Intel
31
Figure 2. Intel
32
Figure 3. Intel
33
Figure 4. Intel
34
North AHB
35
2.1.1.1 ARM
36
Compatibility
36
2.1.1.3 Memory Management
37
2.1.1.4 Instruction Cache
37
2.1.1.5 Branch Target Buffer
37
2.1.1.6 Data Cache
37
2.1.1.7 Intel XScale
38
2.3 Internal Bus
39
2.4 MII Interfaces
39
2.5 AHB Queue Manager
39
2.6 UTOPIA 2
40
2.7 USB v1.1
40
2.9 Memory Controller
40
2.10 Expansion Bus
41
2.13 GPIO
42
2.14 Interrupt Controller
42
2.15 Timers
42
2.16 JTAG
43
3.0 Intel XScale
44
Processor
44
3.1.1 Memory Attributes
45
3.1.3 MMU Control
48
3.1.3.2 Enabling/Disabling
48
3.1.3.3 Locking Entries
49
3.2 Instruction Cache
52
Example: 32K byte cache
53
3.3 Branch Target Buffer
58
History
59
Bits[1:0]
59
3.4 Data Cache
60
Example: 32-Kbyte cache
61
Example: 2K byte cache
62
3.4.2 Cacheability
63
Example 11. Creating Data RAM
70
3.5 Configuration
73
3.5.1 CP15 Registers
75
3.5.1.5 Register 4: Reserved
80
3.5.2 CP14 Registers
86
3.6 Software Debug
88
3.6.1 Definitions
89
3.6.2 Debug Registers
89
3.6.3 Debug Modes
89
3.6.3.1 Halt Mode
90
3.6.3.2 Monitor Mode
90
3.6.4.2 Halt Mode Bit (H)
91
3.6.4.4 Sticky Abort Bit (SA)
92
3.6.5.1 Halt Mode
93
3.6.5.2 Monitor Mode
94
3.6.6 HW Breakpoint Resources
95
3.6.6.2 Data Breakpoints
96
(TXRXCTRL)
98
’ system
99
3.6.8.2 Overflow Flag (OV)
100
3.6.8.3 Download Flag (D)
100
3.6.9 Transmit Register
101
3.6.10 Receive Register
102
3.6.11 Debug JTAG Access
102
3.6.11.1 SELDCSR JTAG Command
102
3.6.12 Trace Buffer
109
3.6.13 Trace Buffer Entries
111
3.6.13.1 Message Byte
111
3.6.14.1 LDIC JTAG Command
116
3.6.14.3 LDIC Cache Functions
118
Debugger Actions
123
Debug Handler Actions
123
3.7 Performance Monitoring
133
(PMN0 - PMN3)
134
(EVTSEL)
137
3.7.6 Examples
142
3.8 Programming Model
144
3.8.2.2 26-Bit Architecture
145
3.8.2.3 Thumb
145
3.8.2.4 ARM
145
DSP-Enhanced Instruction Set
145
3.8.2.5 Base Register Update
145
3.8.3 Extensions to ARM
146
Architecture
146
3.8.3.2 New Page Attributes
152
3.8.3.4 Event Architecture
154
3.9.1 Interrupt Latency
159
3.9.2 Branch Prediction
160
3.9.3 Addressing Modes
160
3.9.4 Instruction Latencies
160
3.9.4.1 Performance Terms
160
UMLALr6,r8,r0,r1
161
ADD r9,r10,r11
161
SUB r2,r8,r9
161
MOV r0,r1
161
3.10 Optimization Guide
167
3.10.1.1 About This Section
168
3.10.2 Processors’ Pipeline
168
F1 F2 ID RF X1 X2
169
M1 M2 Mx
169
3.10.2.4 Memory Pipeline
172
3.10.3 Basic Optimizations
173
3.10.4.1 Instruction Cache
180
3.10.4.2 Data and Mini Cache
181
3.10.4.3 Cache Considerations
184
3.10.5 Instruction Scheduling
191
3.10.5.1 Scheduling Loads
191
3.10.6 Optimizing C Libraries
199
3.10.7 Optimizations for Size
199
5.0 Internal Bus
204
5.2 Memory Map
205
Table 96. Memory Map
206
6.0 PCI Controller
208
South AHB
210
Figure 33
216
Register
220
Translation
222
Register Name Description
225
6.6.1 PCI Byte Enables
226
0x00000010
227
0x00000110 DATA
228
0x00028F91 DAT
229
0xB 0x0
229
0x00000014
230
0x00000015
232
0x00000014 DATA 0
234
6.13 PCI RCOMP Circuitry
249
6.14 Register Descriptions
249
(PCI_DIDVID)
250
(PCI_SRCR)
250
PCI_SRCR (Sheet 1 of 2)
251
(PCI_BAR0)
253
PCI_BHLC
253
PCI_BAR0
253
(PCI_CRP_WDATA)
261
PCI_CRP_AD_CBE
261
PCI_CRP_WDATA
261
(PCI_ISR)
263
PCI_ISR (Sheet 1 of 2)
263
PCI_CSR (Sheet 2 of 2)
263
(PCI_INTEN)
264
PCI_INTEN
264
PCI_ISR (Sheet 2 of 2)
264
(PCI_DMACTRL)
265
PCI_DMACTRL (Sheet 1 of 2)
265
(PCI_PTADMA0_AHBADDR)
271
(PCI_PTADMA0_PCIADDR)
271
PCI_PTADMA0_AHBADDR
271
7.0 SDRAM Controller
276
B4963-01
277
B4964-01
278
7.1 SDRAM Memory Space
279
7.2.1 Initializing the SDRAM
283
7.3 SDRAM Memory Accesses
285
7.3.2 Write Transfer
286
7.3.2.1 Write Transfer
286
7.4 Register Description
287
7.4.2 Refresh Register
288
7.4.3 Instruction Register
288
SDR_CONFIG
288
SDR_REFRESH
288
SDRAM controller:
289
Table 116. SDRAM Commands
290
8.0 Expansion Bus Controller
292
(9+CNFG[3:0])
295
8.6 Using I/O Wait
301
Valid Data
302
Valid Address
302
8.8.1 Intel
305
8.8.2 Intel
306
Multiplexed-Mode Read Access
306
8.8.3 Intel
307
Simplex-Mode Write Access
307
8.8.4 Intel
308
Simplex-Mode Read Access
308
T1 T2 T3 T4 T5
311
Motorola* Simplex
311
Write Mode
311
Motorola* Simplex
312
Read Mode
312
8.8.9 TI* HPI-8 Write Access
313
8.8.10 TI* HPI-8 Read Access
314
8.9 Register Descriptions
319
BYTE_SWAP_EN
325
9.0 AHB/APB Bridge
328
Figure 77. APB Interface
329
Peripheral
330
TXD or RXD
333
Bit Definition
333
Figure 79. UART Block Diagram
334
10.2 Configuring the UART
335
10.2.4 UART Interrupts
339
10.4 Register Descriptions
344
Modem Control Register
346
10.4.7 FIFO Control Register
349
10.4.8 Line Control Register
350
10.4.9 Modem Control Register
352
10.4.10 Line Status Register
353
LSR (Sheet 1 of 2)
353
10.4.11 Modem Status Register
354
LSR (Sheet 2 of 2)
354
10.4.12 Scratch-Pad Register
355
ISR (Sheet 1 of 2)
356
10.5 Console UART
357
Interrupt Mask:
365
ISR (Sheet 2 of 2)
370
11.1 Initializing the IBPMU
372
11.2 Using the IBPMU
373
11.2.2 Monitored SDRAM Events
377
11.2.3 Cycle Count
377
11.3 Register Descriptions
378
PSMR (Sheet 1 of 2)
384
PSMR (Sheet 2 of 2)
385
-MHz clock cycles before an
388
12.4 Register Description
391
(GPIT2R)
394
GPIT2R (Sheet 1 of 2)
394
12.4.7 GPIO Clock Register
395
(GPCLKR)
395
GPIT2R (Sheet 2 of 2)
395
GPCLKR (Sheet 1 of 2)
395
GPCLKR (Sheet 2 of 2)
396
13.0 Interrupt Controller
398
13.4 Reading Interrupt Status
400
INTR_ST (Sheet 1 of 2)
402
INTR_ST (Sheet 2 of 2)
403
13.5.4 IRQ Status Register
404
13.5.5 FIQ Status Register
404
INTR_PRTY
405
INTR_IRQ_ENC_ST
406
INTR_FIQ_ENC_ST
406
14.0 Timers
408
14.2 Time-Stamp Timer
409
14.3 General-Purpose Timers
409
14.4.1 Time-Stamp Timer
411
OST_TIM0
411
OST_TIM0_RL
412
OST_TIM1
412
14.4.6 Watch-Dog Timer
413
OST_TIM1_RL
413
OST_WDOG
413
14.4.8 Watch-Dog Key Register
414
OST_WDOG_ENAB
414
OST_WDOG_KEY
414
14.4.9 Timer Status
415
OST_STATUS
415
15.0 Ethernet MAC A
416
15.1 Ethernet Coprocessor
417
15.2 Register Descriptions
427
15.2.1 Transmit Control 1
428
15.2.2 Transmit Control 2
429
15.2.3 Receive Control 1
429
15.2.4 Receive Control 2
430
15.2.5 Random Seed
430
15.2.13 Slot Time
433
15.2.15 MDIO Command 1
434
15.2.16 MDIO Command 2
434
15.2.17 MDIO Command 3
435
15.2.18 MDIO Command 4
435
15.2.19 MDIO Status Registers
435
MDIO Command
435
15.2.20 MDIO Status 1
436
15.2.21 MDIO Status 2
436
15.2.22 MDIO Status 3
436
15.2.23 MDIO Status 4
436
15.2.25 Address Mask 1
437
15.2.26 Address Mask 2
438
15.2.27 Address Mask 3
438
15.2.28 Address Mask 4
438
15.2.29 Address Mask 5
438
15.2.30 Address Mask 6
439
15.2.31 Address Registers
439
15.2.32 Address 1
440
15.2.33 Address 2
440
15.2.34 Address 3
440
15.2.35 Address 4
440
15.2.36 Address 5
441
15.2.37 Address 6
441
15.2.40 Unicast Address 1
443
15.2.41 Unicast Address 2
443
15.2.42 Unicast Address 3
443
15.2.43 Unicast Address 4
443
15.2.44 Unicast Address 5
444
15.2.45 Unicast Address 6
444
15.2.46 Core Control
444
16.0 Ethernet MAC B
446
Correct interval
454
Data from here is processed
454
17.5.1 HSS Clock and Jitter
455
Characterization
456
PeriodPeriodPj −=
457
17.6.2 E1
459
17.6.3 MVIP
460
Timeslots
463
MHz clock
463
Frame pulse
463
B4252-02
464
Unused Bytes
465
18.1 USB Overview
468
18.2 Device Configuration
469
18.3 USB Operation
470
18.3.2 Bit Encoding
471
18.3.3 Field Formats
472
The presence of SOF
474
18.3.5 Transaction Formats
475
18.3.6 UDC Device Requests
477
18.3.7 UDC Configuration
478
18.4 UDC Hardware Connections
479
18.5 Register Descriptions
479
18.5.1.1 UDC Enable
481
18.5.1.2 UDC Active
481
18.5.1.3 UDC Resume (RSM)
481
0 x 00000000
485
18.5.3.3 Flush Tx FIFO (FTF)
486
18.5.3.5 Sent STALL (SST)
486
18.5.3.6 Force STALL (FST)
486
18.5.3.7 Bit 6 Reserved
487
18.5.7.3 Flush Tx FIFO (FTF)
494
18.5.7.5 Sent STALL (SST)
494
18.5.7.6 Force STALL (FST)
494
18.5.7.7 Bit 6 Reserved
494
(UDCCS6)
495
18.5.8.7 Bit 6 Reserved
497
UDCCS7 (Sheet 1 of 2)
499
18.5.10.6 Bit 5 Reserved
501
18.5.10.7 Bit 6 Reserved
501
18.5.12.3 Flush Tx FIFO (FTF)
504
18.5.12.5 Sent STALL (SST)
504
18.5.12.6 Force STALL (FST)
504
18.5.12.7 Bit 6 Reserved
504
18.5.13.7 Bit 6 Reserved
507
UDCCS11 (Sheet 1 of 2)
507
18.5.14.6 Force Stall (FST)
509
18.5.15.3 Flush Tx FIFO (FTF)
510
UDCCS14 (Sheet 1 of 2)
513
18.5.17.3 Flush Tx FIFO (FTF)
514
UDCCS14 (Sheet 2 of 2)
514
18.5.17.5 Sent STALL (SST)
515
18.5.17.6 Force STALL (FST)
515
18.5.17.7 Bit 6 Reserved
515
Access: Read/Write
518
18.5.41 UDC Data Register 11
535
(UDDR11)
535
processor writes
537
19.0 UTOPIA Level-2
538
19.1 UTOPIA Transmit Module
540
19.2 UTOPIA Receive Module
543
(a.k.a. – RX_CLAV)
545
(a.k.a. – RX_ENB_N)
545
19.4 MPHY Polling Routines
546
19.5 UTOPIA Level-2 Clocks
546
20.0 JTAG Interface
548
20.1.1 Test-Logic-Reset State
549
20.1.2 Run-Test/Idle State
550
20.1.3 Select-DR-Scan State
550
20.1.4 Capture-DR State
550
20.1.5 Shift-DR State
550
20.1.6 Exit1-DR State
551
20.1.7 Pause-DR State
551
20.1.8 Exit2-DR State
551
20.1.9 Update-DR State
551
20.1.10 Select-IR-Scan State
552
20.1.11 Capture-IR State
552
20.1.12 Shift-IR State
552
20.1.13 Exit1-IR State
552
20.1.14 Pause-IR State
552
20.2 JTAG Instructions
553
20.3 Data Registers
554
20.3.1 Boundary Scan Register
555
20.3.2 Instruction Register
555
21.0 AHB Queue Manager (AQM)
556
21.3 Functional Description
557
21.4 AHB Interface
558
21.4.1 Queue Control
559
21.4.2 Queue Status
560
21.4.2.1 Status Update
560
21.4.2.2 Flag Bus
561
21.5 Register Descriptions
562
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