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Intel 253666-024US Handbücher

Bedienungsanleitungen und Benutzerhandbücher für Hardware Intel 253666-024US.
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Intel 253666-024US Bedienungsanleitung (760 Seiten)


Marke: Intel | Kategorie: Hardware | Größe: 2.52 MB |

 

Inhaltsverzeichnis

Software Developer’s Manual

1

Vol. 2A v

5

Vol. 2A vii

7

Vol. 2A ix

9

Vol. 2A xi

11

Vol. 2A xiii

13

Vol. 2A xv

15

Vol. 2A xvii

17

Vol. 2A xix

19

CONTENTS

20

CHAPTER 1

21

ABOUT THIS MANUAL

21

1-2 Vol. 2A

22

1.3 NOTATIONAL CONVENTIONS

23

1.3.1 Bit and Byte Order

24

1.3.3 Instruction Operands

26

1.3.5 Segmented Addressing

26

1.3.6 Exceptions

27

1.4 RELATED LITERATURE

28

Vol. 2A 1-9

29

1-10 Vol. 2A

30

CHAPTER 2

31

INSTRUCTION FORMAT

31

• Group 2

32

• Group 3

32

• Group 4

32

2.1.2 Opcodes

33

2.1.3 ModR/M and SIB Bytes

34

Vol. 2A 2-5

35

2-6 Vol. 2A

36

Vol. 2A 2-7

37

2-8 Vol. 2A

38

2.2.1 REX Prefixes

39

2.2.1.1 Encoding

40

5UUU %EEE

41

2-12 Vol. 2A

42

2.2.1.3 Displacement

43

2.2.1.5 Immediates

44

• Near branches

45

CHAPTER 3

47

3-2 Vol. 2A

48

3-4 Vol. 2A

50

Vol. 2A 3-5

51

3-6 Vol. 2A

52

3.1.1.7 Operation Section

53

3-8 Vol. 2A

54

Vol. 2A 3-9

55

3-10 Vol. 2A

56

Vol. 2A 3-11

57

Intrinsics API

58

Technology Intrinsics

58

Vol. 2A 3-13

59

3-14 Vol. 2A

60

Vol. 2A 3-15

61

3-16 Vol. 2A

62

Vol. 2A 3-17

63

3.2 INSTRUCTIONS (A-M)

64

ADC—Add with Carry

73

Vol. 2A 3-35

81

Vol. 2A 3-39

85

Vol. 2A 3-41

87

xmm2/m128[63:0];

92

AND—Logical AND

99

Description

100

Operation

100

Flags Affected

100

Protected Mode Exceptions

100

Real-Address Mode Exceptions

100

Virtual-8086 Mode Exceptions

101

Compatibility Mode Exceptions

101

64-Bit Mode Exceptions

101

Point Values

102

Floating-Point Values

106

Vol. 2A 3-65

111

BSF—Bit Scan Forward

115

BSR—Bit Scan Reverse

117

BSWAP—Byte Swap

119

BT—Bit Test

121

BTC—Bit Test and Complement

124

BTR—Bit Test and Reset

127

BTS—Bit Test and Set

130

CALL—Call Procedure

133

Vol. 2A 3-89

135

Vol. 2A 3-91

137

-byte call gate

138

= 16 *)

140

Vol. 2A 3-95

141

≠ CPL)

142

Vol. 2A 3-97

143

≠ DPL of code segment

144

Vol. 2A 3-99

145

Vol. 2A 3-105

151

CLC—Clear Carry Flag

152

CLD—Clear Direction Flag

153

CLFLUSH—Flush Cache Line

154

Vol. 2A 3-109

155

CLI — Clear Interrupt Flag

156

Vol. 2A 3-111

157

< 3) AND (VME = 1)

157

Vol. 2A 3-113

159

CMC—Complement Carry Flag

161

CMOVcc—Conditional Move

162

Vol. 2A 3-117

163

Vol. 2A 3-119

165

CMP—Compare Two Operands

169

Vol. 2A 3-127

173

Vol. 2A 3-135

181

Vol. 2A 3-139

185

CMPXCHG—Compare and Exchange

196

Values and Set EFLAGS

202

CPUID—CPU Identification

208

Vol. 2A 3-163

209

Vol. 2A 3-165

211

Vol. 2A 3-167

213

• Model — 1111B

215

• Family — 0101B

215

• Processor Type — 00B

215

Processor 01B

216

Vol. 2A 3-171

217

OM16524b

218

Vol. 2A 3-173

219

(';

220

Vol. 2A 3-175

221

Vol. 2A 3-177

223

Vol. 2A 3-179

225

-μop, 8-way set associative

226

Vol. 2A 3-181

227

How Brand Strings Work

228

Vol. 2A 3-183

229

III Xeon

230

Vol. 2A 3-187

233

Vol. 2A 3-189

235

Packed Doubleword Integers

241

Vol. 2A 3-197

243

Vol. 2A 3-215

261

Doubleword Integer

265

Floating-Point Value

271

Vol. 2A 3-233

279

Vol. 2A 3-245

291

Quadword

301

Vol. 2A 3-257

303

> 9) or AF = 1)

303

Vol. 2A 3-259

305

DEC—Decrement by 1

307

Vol. 2A 3-263

309

DIV—Unsigned Divide

310

Table 3-20. DIV Action

311

Vol. 2A 3-271

317

Vol. 2A 3-273

319

Vol. 2A 3-279

325

ELSE IF StackSize = 32

329

ELSE (* StackSize = 16 *)

329

1 to (NestingLevel - 1)

329

F2XM1—Compute 2

332

FABS—Absolute Value

334

FADD/FADDP/FIADD—Add

336

= FADDP

337

FPU Flags Affected

338

Floating-Point Exceptions

338

Table 3-24. FBSTP Results

342

FCHS—Change Sign

345

FCLEX/FNCLEX—Clear Exceptions

347

Set EFLAGS

355

Vol. 2A 3-311

357

FCOS—Cosine

358

Vol. 2A 3-313

359

FDIV/FDIVP/FIDIV—Divide

362

Vol. 2A 3-317

363

= FDIVP

364

= FIDIVR

367

= FDIVRP

368

FICOM/FICOMP—Compare Integer

371

= FICOMP

372

FILD—Load Integer

374

Vol. 2A 3-333

379

FIST/FISTP—Store Integer

380

= FISTP

381

← not roundup; 1 ← roundup

381

Vol. 2A 3-337

383

Numeric Exceptions

385

Real Address Mode Exceptions

385

Virtual 8086 Mode Exceptions

385

FLD—Load Floating Point Value

387

Vol. 2A 3-345

391

FMUL/FMULP/FIMUL—Multiply

397

= FMULP

398

FNOP—No Operation

401

FPATAN—Partial Arctangent

402

Vol. 2A 3-357

403

FPREM—Partial Remainder

405

Vol. 2A 3-361

407

FPREM1—Partial Remainder

408

FPTAN—Partial Tangent

411

FRNDINT—Round to Integer

414

FRSTOR—Restore x87 FPU State

416

FSCALE—Scale

423

3-378 Vol. 2A FSCALE—Scale

424

FSIN—Sine

425

3-380 Vol. 2A FSIN—Sine

426

FSINCOS—Sine and Cosine

427

FSQRT—Square Root

430

Vol. 2A 3-391

437

Vol. 2A 3-393

439

FSUB/FSUBP/FISUB—Subtract

444

= result)

445

− DEST; FI;

449

FSUBRP

450

FTST—TEST

452

= SRC: C3, C2, C0 ← 100;

455

= FUCOMP

455

= FUCOMPP

455

FXAM—ExamineModR/M

457

Non-64-Bit Mode Operation

464

Memory Region

464

Memory Region (Contd.)

465

Vol. 2A 3-421

467

IA-32e Mode Operation

469

Default OperandSize

470

Default OperandSize (Contd.)

471

Implementation Note

474

FYL2X—Compute y ∗ log

477

FYL2XP1—Compute y ∗ log

479

Exceptions

486

HLT—Halt

489

− xmm1[127:64];

492

− xmm2/m128[127:64];

492

If the LOCK prefix is used

494

− xmm1[63:32];

496

−xmm1[127:96];

496

− xmm2/m128[63:32];

496

− xmm2/m128[127:96];

496

IDIV—Signed Divide

499

= 8 (* Word/byte operation *)

500

IMUL—Signed Multiply

503

IN—Input from Port

508

Vol. 2A 3-463

509

INC—Increment by 1

510

Table 3-56. Decision Table

518

= 1, task gate *)

520

Vol. 2A 3-475

521

Vol. 2A 3-477

523

≠ DPL of code segment

525

= 0; FI;

525

Vol. 2A 3-485

531

INVLPG—Invalidate TLB Entry

534

IRET/IRETD—Interrupt Return

536

Vol. 2A 3-493

539

Vol. 2A 3-495

541

Vol. 2A 3-497

543

Jcc—Jump if Condition Is Met

547

Vol. 2A 3-503

549

JMP—Jump

554

Vol. 2A 3-509

555

• A task switch

556

3-512 Vol. 2A JMP—Jump

558

Vol. 2A 3-513

559

3-514 Vol. 2A JMP—Jump

560

Vol. 2A 3-517

563

LAR—Load Access Rights Byte

566

≠ conforming code segment

568

Implementation Notes

570

LDMXCSR—Load MXCSR Register

573

= NULL and ( (RPL = 3) or

576

≠ 3 and RPL ≠ CPL) )

576

Vol. 2A 3-531

577

LEA—Load Effective Address

581

= 16 and AddressSize = 16

582

= 16 and AddressSize = 32

582

= 32 and AddressSize = 16

582

= 32 and AddressSize = 32

582

= 16 and AddressSize = 64

582

= 32 and AddressSize = 64

583

= 64 and AddressSize = 64

583

Vol. 2A 3-539

585

LFENCE—Load Fence

586

Vol. 2A 3-545

591

LMSW—Load Machine Status Word

593

LSL—Load Segment Limit

604

= 64 (* REX.W used *)

606

LTR—Load Task Register

608

Vol. 2A 3-563

609

Vol. 2A 3-569

615

> SRC[31:0]); FI;

620

> SRC[127:96])

620

= SNaN)

623

= SNaN) THEN SRC[31:0]; FI;

626

MFENCE—Memory Fence

629

< SRC[63:0])

630

> SRC[31:0])

633

< SRC[127:96])

633

= SNaN) THEN SRC[63:0]; FI;

636

Vol. 2A 3-597

643

MOV—Move

645

Vol. 2A 3-609

655

#UD If CR0.EM[bit 2] = 1

658

If CR4.OSFXSR[bit 9] = 0

658

Vol. 2A 3-619

665

Vol. 2A 3-637

683

#UD If CR0.EM[bit 2] = 1

697

Non-Temporal Hint

700

MOVQ—Move Quadword

709

String to String

714

MOVZX—Move with Zero-Extend

739

MUL—Unsigned Multiply

741

Vol. 2A 3-701

747

Vol. 2A 3-703

749

Vol. 2A 3-707

753

Vol. 2A 3-709

755

MWAIT—Monitor Wait

756

MWAIT for Power Management

757




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