Intel 815E Bedienungsanleitung PDF herunterladen (Seite 56)

User’s Manual

46 ECB-865 User’s Manual

3.11.38.2 System

CLK

Clock provides timing for all transactions on PCI and is an input to every PCI device.

All other PCI signals, except RST#, INTA#, INTB#, INTC#, and INTD#, are sampled

on the rising edge of CLK and all other timing parameters are defined with respect to

this edge. PCI operates up to 33 MHz or 66 MHz and, in general, the minimum

frequency is DC (0 Hz).

RST#

Reset is used to bring PCI-specific registers, sequencers, and signals to a consistent

state. What effect RST# has on a device beyond the PCI sequencer is beyond the

scope of this specification, except for reset states of required PCI configuration

registers. Anytime RST# is asserted, all PCI output signals must be driven to their

benign state. In general, this means they must be asynchronously tri-stated. SERR#

(open drain) is floated. REQ# and GNT# must both be tri-stated (they cannot be

driven low or high during reset). To prevent AD, C/BE#, and PAR signals from

floating during reset, the central resource may drive these lines during reset (bus

parking) but only to a logic low level–they may not be driven high. RST# may be

asynchronous to CLK when asserted or deasserted. Although asynchronous,

deassertion is guaranteed to be a clean, bounce-free edge. Except for configuration

accesses, only devices that are required to boot the system will respond after reset.

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Intel 815E Bedienungsanleitung Seite 56