Intel 815E Bedienungsanleitung PDF herunterladen (Seite 59)

ECB-865

ECB-865 User’s Manual 49

3.11.38.6 Interrupts

PIRQ#

Interrupts on PCI are optional and defined as "level sensitive," asserted low (negative

true), using open drain output drivers. The assertion and deassertion of INTx# is

asynchronous to CLK. A device asserts its INTx# line when requesting attention from

its device driver. Once the INTx# signal is asserted, it remains asserted until the

device driver clears the pending request. When the request is cleared, the device

deasserts its INTx# signal. PCI defines one interrupt line for a single function device

and up to four interrupt lines for a multi-function

7 device or connector. For a single

function device, only INTA# may be used while the other three interrupt lines have no

meaning. PIRQ# is connected to INTB#

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Intel 815E Bedienungsanleitung Seite 59