Intel FF8062701084601 Datenblatt Seite 1

Document Number: 324692-0062nd Generation Intel® Core™ Processor Family Mobile and Intel® Celeron® Processor Family MobileDatasheet, Volume 1Supportin

10 Datasheet, Volume 1

Electrical Specifications100 Datasheet, Volume 1Notes:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2

Datasheet, Volume 1 101Electrical SpecificationsNotes:1. VAUX-DIFFp-p = 2*|VAUXP – VAUXM|. Refer to the VESA DisplayPort Standard specification for mo

Electrical Specifications102 Datasheet, Volume 17.10.2 PECI DC CharacteristicsThe PECI interface operates at a nominal voltage set by VCCIO The set of

Datasheet, Volume 1 103Electrical Specifications7.10.3 Input Device HysteresisThe input buffers in both client and host models must use a Schmitt-trig

Electrical Specifications104 Datasheet, Volume 1

Datasheet, Volume 1 105Processor Pin and Signal Information8 Processor Pin and Signal Information8.1 Processor Pin Assignments• Table 8-1, Table 8-2 a

Processor Pin and Signal Information106 Datasheet, Volume 1Figure 8-1. rPGA988B (Socket-G2) Pinmap (Top View, Upper-Left Quadrant)

Processor Pin and Signal InformationDatasheet, Volume 1 107Figure 8-2. rPGA988B (Socket-G2) Pinmap (Top View, Upper-Right Quadrant)

Processor Pin and Signal Information108 Datasheet, Volume 1Figure 8-3. rPGA988B (Socket-G2) Pinmap (Top View, Lower-Left Quadrant)

Processor Pin and Signal InformationDatasheet, Volume 1 109Figure 8-4. rPGA988B (Socket-G2) Pinmap (Top View, Lower-Right Quadrant)

Datasheet, Volume 1 11Introduction1 IntroductionThe 2nd Generation Intel® Core™ processor family mobile and Intel® Celeron® processor family mobile ar

Processor Pin and Signal Information110 Datasheet, Volume 1Table 8-1. rPGA988B Processor Pin List by Pin Name Pin Name Pin # Buffer Type DirBCLK A28 D

Processor Pin and Signal InformationDatasheet, Volume 1 111PEG_RX#[5] H34 PCIe IPEG_RX#[6] H31 PCIe IPEG_RX#[7] G33 PCIe IPEG_RX#[8] G30 PCIe IPEG_RX#

Processor Pin and Signal Information112 Datasheet, Volume 1RSVD AK32RSVD AK2RSVD AJ32RSVD AJ27RSVD AJ26RSVD_NCTF AT34RSVD_NCTF B35RSVD_NCTF B34RSVD_NC

Processor Pin and Signal InformationDatasheet, Volume 1 113SA_DQ[43] AK9 DDR3 I/OSA_DQ[44] AH8 DDR3 I/OSA_DQ[45] AH9 DDR3 I/OSA_DQ[46] AL9 DDR3 I/OSA_

Processor Pin and Signal Information114 Datasheet, Volume 1SB_DQ[24] M5 DDR3 I/OSB_DQ[25] N4 DDR3 I/OSB_DQ[26] N2 DDR3 I/OSB_DQ[27] N1 DDR3 I/OSB_DQ[2

Processor Pin and Signal InformationDatasheet, Volume 1 115VAXG AH23 PWRVAXG AH24 PWRVAXG AJ17 PWRVAXG AJ18 PWRVAXG AJ20 PWRVAXG AJ21 PWRVAXG AJ23 PWR

Processor Pin and Signal Information116 Datasheet, Volume 1VCC AG28 PWRVCC AG29 PWRVCC AG30 PWRVCC AG31 PWRVCC AG32 PWRVCC AG33 PWRVCC AG34 PWRVCC AG3

Processor Pin and Signal InformationDatasheet, Volume 1 117VCCIO F13 PWRVCCIO F14 PWRVCCIO G13 PWRVCCIO G14 PWRVCCIO H14 PWRVCCIO J13 PWRVCCIO J14 PWR

Processor Pin and Signal Information118 Datasheet, Volume 1VSS AH4 GNDVSS AH7 GNDVSS AJ1 GNDVSS AJ10 GNDVSS AJ13 GNDVSS AJ16 GNDVSS AJ19 GNDVSS AJ2 GN

Processor Pin and Signal InformationDatasheet, Volume 1 119VSS B15 GNDVSS B17 GNDVSS B19 GNDVSS B2 GNDVSS B22 GNDVSS B3 GNDVSS B5 GNDVSS B7 GNDVSS B8

Introduction12 Datasheet, Volume 1Figure 1-1. Mobile Platform System Block Diagram Example

Processor Pin and Signal Information120 Datasheet, Volume 1VSS N30 GNDVSS N31 GNDVSS N32 GNDVSS N33 GNDVSS N34 GNDVSS N35 GNDVSS P2 GNDVSS P3 GNDVSS P

Processor Pin and Signal InformationDatasheet, Volume 1 121Figure 8-5. BGA1224 Ballmap (Top View, Upper-Left Quadrant)

Processor Pin and Signal Information122 Datasheet, Volume 1Figure 8-6. BGA1224 Ballmap (Top View, Upper-Right Quadrant)

Processor Pin and Signal InformationDatasheet, Volume 1 123Figure 8-7. BGA1224 Ballmap (Top View, Lower-Left Quadrant)

Processor Pin and Signal Information124 Datasheet, Volume 1Figure 8-8. BGA1224 Ballmap (Top View, Lower-Right Quadrant)

Processor Pin and Signal InformationDatasheet, Volume 1 125Table 8-2. BGA1224 Processor Ball List by Ball Name Ball Name Ball # Buffer Type DirBCLK D5

Processor Pin and Signal Information126 Datasheet, Volume 1FDI0_FSYNC AC8 CMOS IFDI0_LSYNC AB7 CMOS IFDI0_TX#[0] V7 FDI OFDI0_TX#[1] W8 FDI OFDI0_TX#[

Processor Pin and Signal InformationDatasheet, Volume 1 127PEG_TX[14] D7 PCIe OPEG_TX[15] F13 PCIe OPM_SYNC K53 Asynch CMOS IPRDY# J62 Asynch CMOS OPR

Processor Pin and Signal Information128 Datasheet, Volume 1RSVD H5RSVD G52RSVD G48RSVD G4RSVD F5RSVD D49RSVD D25RSVD D3RSVD C52RSVD C24RSVD C4RSVD B53

Processor Pin and Signal InformationDatasheet, Volume 1 129SA_DQ[61] AY57 DDR3 I/OSA_DQ[62] AN60 DDR3 I/OSA_DQ[63] AR60 DDR3 I/OSA_DQS#[0] AN8 DDR3 I/

Datasheet, Volume 1 13Introduction1.1 Processor Feature Details• Four or two execution cores• A 32-KB instruction and 32-KB data first-level cache (L1

Processor Pin and Signal Information130 Datasheet, Volume 1SB_DQ[35] BG50 DDR3 I/OSB_DQ[36] BF49 DDR3 I/OSB_DQ[37] BH47 DDR3 I/OSB_DQ[38] BF53 DDR3 I/

Processor Pin and Signal InformationDatasheet, Volume 1 131VAXG AF58 PWRVAXG AF56 PWRVAXG AE64 PWRVAXG AE62 PWRVAXG AE60 PWRVAXG AD65 PWRVAXG AD63 PWR

Processor Pin and Signal Information132 Datasheet, Volume 1VCC L40 PWRVCC L38 PWRVCC L34 PWRVCC L32 PWRVCC L28 PWRVCC L26 PWRVCC L22 PWRVCC K45 PWRVCC

Processor Pin and Signal InformationDatasheet, Volume 1 133VCCDQ AL23 PWRVCCIO AV55 PWRVCCIO AV53 PWRVCCIO AV48 PWRVCCIO AV17 PWRVCCIO AV15 PWRVCCIO A

Processor Pin and Signal Information134 Datasheet, Volume 1VCCSA N16 PWRVCCSA N14 PWRVCCSA M17 PWRVCCSA M15 PWRVCCSA M12 PWRVCCSA M11 PWRVCCSA L18 PWR

Processor Pin and Signal InformationDatasheet, Volume 1 135VSS BJ48 GNDVSS BJ40 GNDVSS BJ32 GNDVSS BJ24 GNDVSS BJ20 GNDVSS BJ16 GNDVSS BJ12 GNDVSS BJ8

Processor Pin and Signal Information136 Datasheet, Volume 1VSS AV63 GNDVSS AV59 GNDVSS AV57 GNDVSS AV50 GNDVSS AV44 GNDVSS AV38 GNDVSS AV31 GNDVSS AV2

Processor Pin and Signal InformationDatasheet, Volume 1 137VSS AF63 GNDVSS AF61 GNDVSS AF11 GNDVSS AF9 GNDVSS AF5 GNDVSS AE57 GNDVSS AD16 GNDVSS AD14

Processor Pin and Signal Information138 Datasheet, Volume 1VSS L12 GNDVSS L8 GNDVSS K39 GNDVSS K33 GNDVSS K27 GNDVSS K1 GNDVSS J64 GNDVSS J60 GNDVSS J

Processor Pin and Signal InformationDatasheet, Volume 1 139VSS_NCTF BH61VSS_NCTF BH5VSS_NCTF BE64VSS_NCTF BE2VSS_NCTF BD65VSS_NCTF BD1VSS_NCTF F65VSS_

Introduction14 Datasheet, Volume 1• Memory organizations— Single-channel modes— Dual-channel modes - Intel® Flex Memory Technology:- Dual-channel symm

Processor Pin and Signal Information140 Datasheet, Volume 1Figure 8-9. BGA1023 Ballmap (Top View, Upper-Left Quadrant)

Processor Pin and Signal InformationDatasheet, Volume 1 141Figure 8-10. BGA1023 Ballmap (Top View, Upper-Right Quadrant)

Processor Pin and Signal Information142 Datasheet, Volume 1Figure 8-11. BGA1023 Ballmap (Top View, Lower-Left Quadrant)

Processor Pin and Signal InformationDatasheet, Volume 1 143Figure 8-12. BGA1023 Ballmap (Top View, Lower-Right Quadrant)

Processor Pin and Signal Information144 Datasheet, Volume 1Table 8-3. BGA1023 Processor Ball List by Ball Name Ball Name Ball # Buffer Type DirBCLK J3

Processor Pin and Signal InformationDatasheet, Volume 1 145FDI0_TX[2] W3 FDI OFDI0_TX[3] AA7 FDI OFDI1_FSYNC AC12 CMOS IFDI1_LSYNC AG8 CMOS IFDI1_TX#[

Processor Pin and Signal Information146 Datasheet, Volume 1RSVD BE7RSVD BD26RSVD BD25RSVD BD22RSVD BD21RSVD BB21RSVD BB19RSVD BA22RSVD BA19RSVD AY22RS

Processor Pin and Signal InformationDatasheet, Volume 1 147SA_DQ[49] AV56 DDR3 I/OSA_DQ[50] AP50 DDR3 I/OSA_DQ[51] AP53 DDR3 I/OSA_DQ[52] AV54 DDR3 I/

Processor Pin and Signal Information148 Datasheet, Volume 1SB_DQ[31] BF19 DDR3 I/OSB_DQ[32] BD50 DDR3 I/OSB_DQ[33] BF48 DDR3 I/OSB_DQ[34] BD53 DDR3 I/

Processor Pin and Signal InformationDatasheet, Volume 1 149VAXG AB59 PWRVAXG AB58 PWRVAXG AB56 PWRVAXG AB55 PWRVAXG AB53 PWRVAXG AB52 PWRVAXG AB51 PWR

Datasheet, Volume 1 15Introduction• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering)• Peer segment destination posted

Processor Pin and Signal Information150 Datasheet, Volume 1VCC E38 PWRVCC E37 PWRVCC E34 PWRVCC E32 PWRVCC E28 PWRVCC E26 PWRVCC D42 PWRVCC D39 PWRVCC

Processor Pin and Signal InformationDatasheet, Volume 1 151VCCSA U15 PWRVCCSA R21 PWRVCCSA R18 PWRVCCSA R16 PWRVCCSA P20 PWRVCCSA P17 PWRVCCSA N22 PWR

Processor Pin and Signal Information152 Datasheet, Volume 1VSS AW13 GNDVSS AW7 GNDVSS AV55 GNDVSS AV48 GNDVSS AV40 GNDVSS AV34 GNDVSS AV22 GNDVSS AV21

Processor Pin and Signal InformationDatasheet, Volume 1 153VSS AF55 GNDVSS AF53 GNDVSS AF52 GNDVSS AF51 GNDVSS AF50 GNDVSS AF48 GNDVSS AF47 GNDVSS AF2

Processor Pin and Signal Information154 Datasheet, Volume 1VSS L22 GNDVSS L20 GNDVSS L16 GNDVSS K51 GNDVSS K21 GNDVSS K11 GNDVSS K8 GNDVSS J55 GNDVSS

Datasheet, Volume 1 155Processor Pin and Signal Information8.2 Package Mechanical InformationFigure 8-13. Processor rPGA988B 2C (GT2) Mechanical Packa

Processor Pin and Signal Information156 Datasheet, Volume 1Figure 8-14. Processor rPGA988B 2C (GT2) Mechanical Package (Sheet 2 of 2)

Datasheet, Volume 1 157Processor Pin and Signal InformationFigure 8-15. Processor rPGA988B 4C (GT2) Mechanical Package (Sheet 1 of 2)

Processor Pin and Signal Information158 Datasheet, Volume 1Figure 8-16. Processor rPGA988B 4C (GT2) Mechanical Package (Sheet 2 of 2)

Datasheet, Volume 1 159Processor Pin and Signal InformationFigure 8-17. Processor BGA1023 2C (GT2) Mechanical Package (Sheet 1 of 2)

Introduction16 Datasheet, Volume 1• Supports the following traffic types to or from the PCH— DMI -> DRAM— DMI -> processor core (Virtual Legacy

Processor Pin and Signal Information160 Datasheet, Volume 1Figure 8-18. Processor BGA1023 2C (GT2) Mechanical Package (Sheet 2 of 2)

Datasheet, Volume 1 161Processor Pin and Signal InformationFigure 8-19. Processor BGA1224 4C (GT2) Mechanical Package (Sheet 1 of 2)

Processor Pin and Signal Information162 Datasheet, Volume 1Figure 8-20. Processor BGA1224 4C (GT2) Mechanical Package (Sheet 2 of 2)

Datasheet, Volume 1 163Processor Pin and Signal InformationFigure 8-21. Processor rPGA988B 2C (GT1) Mechanical Package (Sheet 1 of 2)

Processor Pin and Signal Information164 Datasheet, Volume 1Figure 8-22. Processor rPGA988B 2C (GT1) Mechanical Package (Sheet 2 of 2)

Datasheet, Volume 1 165Processor Pin and Signal InformationFigure 8-23. Processor BGA1023 2C (GT1) Mechanical Package (Sheet 1 of 2)

Processor Pin and Signal Information166 Datasheet, Volume 1§ §Figure 8-24. Processor BGA1023 2C (GT1) Mechanical Package (Sheet 2 of 2)

Datasheet, Volume 1 167DDR Data Swizzling9 DDR Data SwizzlingTo achieve better memory performance and better memory timing; Intel design performed the

DDR Data Swizzling168 Datasheet, Volume 1Table 9-1. DDR Data Swizzling Table – Channel APin NamePin Number rPGAPin Number BGA1023Pin Number BGA1224MC

DDR Data SwizzlingDatasheet, Volume 1 169§ §Table 9-2. DDR Data Swizzling Table – Channel BPin NamePin NumberrPGAPin Number BGA1023Pin Number BGA1224M

Datasheet, Volume 1 17Introduction1.2.6 Embedded DisplayPort* (eDP)• Stand alone dedicated port (unlike previous generation processor that shared pins

DDR Data Swizzling170 Datasheet, Volume 1

Introduction18 Datasheet, Volume 11.3.6 Processor Graphics Controller• Intel® Rapid Memory Power Management (Intel® RMPM) – CxSR• Intel® Graphics Perf

Datasheet, Volume 1 19IntroductionExecute Disable BitThe Execute Disable bit allows memory to be marked as executable or non-executable, when combined

2 Datasheet, Volume 1Legal Lines and DisclaimersINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMP

Introduction20 Datasheet, Volume 11.7 Related DocumentsRefer to Table 1-3 for additional information. § §VCCProcessor core power supply.VCCIOHigh Freq

Datasheet, Volume 1 21Interfaces2 InterfacesThis chapter describes the interfaces supported by the processor. 2.1 System Memory Interface2.1.1 System

Interfaces22 Datasheet, Volume 12.1.2 System Memory Timing SupportThe IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and command

Datasheet, Volume 1 23Interfaces2.1.3.2.1 Dual-Channel Symmetric Mode Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum pe

Interfaces24 Datasheet, Volume 12.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)The following sections describe the Just-in-Tim

Datasheet, Volume 1 25Interfaces2.2 PCI Express* InterfaceThis section describes the PCI Express interface capabilities of the processor. See the PCI

Interfaces26 Datasheet, Volume 1through the other layers, they are extended with additional information necessary to handle packets at those layers. A

Datasheet, Volume 1 27Interfaces2.2.2 PCI Express* Configuration MechanismThe PCI Express (external graphics) link is mapped through a PCI-to-PCI brid

Interfaces28 Datasheet, Volume 12.2.4 PCI Express* Lanes ConnectionFigure 2-5 demonstrates the PCIe lanes mapping.2.3 Direct Media Interface (DMI)Dire

Datasheet, Volume 1 29Interfaces2.3.3 DMI Link DownThe DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to data link dow

Datasheet, Volume 1 3Contents1 Introduction ...

Interfaces30 Datasheet, Volume 12.4.1 3D and Video Engines for Graphics ProcessingThe 3D graphics pipeline architecture simultaneously operates on dif

Datasheet, Volume 1 31Interfaces2.4.1.2.6 Windower/IZ (WIZ) StageThe WIZ unit performs an early depth test, which removes failing pixels and eliminate

Interfaces32 Datasheet, Volume 12.4.2 Processor Graphics DisplayThe Processor Graphics controller display pipe can be broken down into three component

Datasheet, Volume 1 33Interfaces2.4.2.1.3 Cursors A and BCursors A and B are small, fixed-sized planes dedicated for mouse cursor acceleration, and ar

Interfaces34 Datasheet, Volume 12.4.4 Multi-Graphics Controller Multi-Monitor SupportThe processor supports simultaneous use of the Processor Graphics

Datasheet, Volume 1 35Technologies3 TechnologiesThis chapter provides a high-level description of Intel technologies implemented in the processor.The

Technologies36 Datasheet, Volume 13.1.2 Intel® Virtualization Technology (Intel® VT) forIA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Feature

Datasheet, Volume 1 37Technologies3.1.4 Intel® Virtualization Technology (Intel® VT) for DirectedI/O (Intel® VT-d) FeaturesThe processor supports the

Technologies38 Datasheet, Volume 13.2 Intel® Trusted Execution Technology (Intel® TXT)Intel Trusted Execution Technology (Intel TXT) defines platform-

Datasheet, Volume 1 39Technologies3.4 Intel® Turbo Boost TechnologyCompared with previous generation products, Intel Turbo Boost Technology will incre

4 Datasheet, Volume 12.4.1 3D and Video Engines for Graphics Processing ... 302.4.1.1 3D Engine Execution Unit

Technologies40 Datasheet, Volume 13.4.2 Intel® Turbo Boost Technology Graphics FrequencyThe graphics render frequency is selected dynamically based on

Datasheet, Volume 1 41Technologies3.6.1 PCLMULQDQ InstructionThe processor supports the carry-less multiplication instruction, PCLMULQDQ. PCLMULQDQ is

Technologies42 Datasheet, Volume 1• More efficient MSR interface to access APIC registers— To enhance inter-processor and self directed interrupt deli

Datasheet, Volume 1 43Power Management4 Power ManagementThis chapter provides information on the following power management topics: • Advanced Configu

Power Management44 Datasheet, Volume 14.1 Advanced Configuration and Power Interface (ACPI) States SupportedThe ACPI states supported by the processor

Datasheet, Volume 1 45Power Management4.1.4 PCI Express* Link States4.1.5 Direct Media Interface (DMI) States 4.1.6 Processor Graphics Controller Stat

Power Management46 Datasheet, Volume 14.2 Processor Core Power ManagementWhile executing code, Enhanced Intel SpeedStep Technology optimizes the proce

Datasheet, Volume 1 47Power Management4.2.2 Low-Power Idle StatesWhen the processor is idle, low-power idle states (C-states) are used to save power.

Power Management48 Datasheet, Volume 1Note: If enabled, the core C-state will be C1E if all cores have resolved a core C1 state or higher.4.2.3 Reques

Datasheet, Volume 1 49Power Management4.2.4 Core C-statesThe following are general rules for all core C-states, unless specified otherwise:• A core C-

Datasheet, Volume 1 54.2.4.4 Core C6 State... 494.2.4.5 Core C7 State...

Power Management50 Datasheet, Volume 14.2.4.6 C-State Auto-DemotionIn general, deeper C-states such as C6 or C7 have long latencies and have higher en

Datasheet, Volume 1 51Power ManagementNote: If enabled, the package C-state will be C1E if all cores have resolved a core C1 state or higher.4.2.5.1 P

Power Management52 Datasheet, Volume 14.2.5.2 Package C1/C1ENo additional power reduction actions are taken in the package C1 state. However, if the C

Datasheet, Volume 1 53Power Management4.2.5.5 Package C7 StateThe processor enters the package C7 low power state when all cores are in the C7 state a

Power Management54 Datasheet, Volume 14.3.2 DRAM Power Management and InitializationThe processor implements extensive support for power management on

Datasheet, Volume 1 55Power ManagementSelection of power modes should be according to power-performance or thermal trade-offs of a given system:• When

Power Management56 Datasheet, Volume 14.3.2.3 Dynamic Power-down OperationDynamic power-down of memory is employed during normal operation. Based on i

Datasheet, Volume 1 57Power Management4.6 Graphics Power Management4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM) (also known as CxSR)The In

Power Management58 Datasheet, Volume 14.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT) Intel S2DDT reduces display refresh memory traffic by re

Datasheet, Volume 1 59Power Management4.6.7 Automatic Display Brightness (ADB)This is a mobile only supported power management feature.Intel® Automati

6 Datasheet, Volume 16.5 Embedded DisplayPort* (eDP) Signals ... 796.6 Intel® Flexible D

Power Management60 Datasheet, Volume 1

Datasheet, Volume 1 61Thermal Management5 Thermal ManagementThe thermal solution provides both the component-level and the system-level thermal manage

Thermal Management62 Datasheet, Volume 15.2.1 Intel® Turbo Boost Technology Power Control and ReportingWhen operating in the turbo mode, the processor

Datasheet, Volume 1 63Thermal Management5.2.2 Package Power Control The package power control allows for customization to implement optimal turbo with

Thermal Management64 Datasheet, Volume 15.3 Thermal and Power SpecificationsThe following notes apply to Table 5-1, Table 5-2, Table 5-3, and Table 5-

Datasheet, Volume 1 65Thermal ManagementTable 5-1. Thermal Design Power (TDP) Specifications Segment StateCPU Core FrequencyProcessor Graphics Core fr

Thermal Management66 Datasheet, Volume 1Quad Core SVTurbo Time Parameter (package)Processor turbo long duration time window (POWER_LIMIT_1_TIME in TUR

Datasheet, Volume 1 67Thermal Management5.4 Thermal Management FeaturesThis section covers thermal management features for the processor.5.4.1 Process

Thermal Management68 Datasheet, Volume 1The Adaptive Thermal Monitor can be activated when any package temperature, monitored by a digital thermal sen

Datasheet, Volume 1 69Thermal ManagementOnce a target frequency/bus ratio is resolved, the processor core will transition to the new target automatica

Datasheet, Volume 1 7Figures1-1 Mobile Platform System Block Diagram Example ... 122-1 Intel® Fl

Thermal Management70 Datasheet, Volume 15.4.1.1.2 Clock ModulationIf the frequency/voltage changes are unable to end an Adaptive Thermal Monitor event

Datasheet, Volume 1 71Thermal ManagementThe DTS-relative temperature readout directly impacts the Adaptive Thermal Monitor trigger point. When a packa

Thermal Management72 Datasheet, Volume 15.4.1.3.2 Voltage Regulator ProtectionPROCHOT# may be used for thermal protection of voltage regulators (VR).

Datasheet, Volume 1 73Thermal Managementenabled. For more details on the interrupt mechanism, refer to the Intel® 64 and IA-32 Architectures Software

Thermal Management74 Datasheet, Volume 15.4.4 Platform Environment Control Interface (PECI)The Platform Environment Control Interface (PECI) is a one-

Datasheet, Volume 1 75Signal Description6 Signal DescriptionThis chapter describes the processor signals. They are arranged in functional groups accor

Signal Description76 Datasheet, Volume 16.1 System Memory Interface SignalsTable 6-2. Memory Channel A Signals Signal Name Description Direction/Buffe

Datasheet, Volume 1 77Signal Description6.2 Memory Reference and Compensation SignalsTable 6-3. Memory Channel B Signals Signal Name Description Direc

Signal Description78 Datasheet, Volume 16.3 Reset and Miscellaneous SignalsTable 6-5. Reset and Miscellaneous Signals Signal Name Description Directio

Datasheet, Volume 1 79Signal Description6.4 PCI Express*-Based Interface Signals6.5 Embedded DisplayPort* (eDP) SignalsTable 6-6. PCI Express* Graphic

8 Datasheet, Volume 14-6 Processor Graphics Controller States ... 454-7 G, S, and

Signal Description80 Datasheet, Volume 16.6 Intel® Flexible Display Interface (Intel® FDI) Signals6.7 Direct Media Interface (DMI) Signals6.8 Phase Lo

Datasheet, Volume 1 81Signal Description6.9 Test Access Points (TAP) Signals6.10 Error and Thermal Protection SignalsTable 6-11. Test Access Points (T

Signal Description82 Datasheet, Volume 16.11 Power Sequencing Signals6.12 Processor Power SignalsTHERMTRIP#Thermal Trip: The processor protects itself

Datasheet, Volume 1 83Signal Description6.13 Sense Signals6.14 Ground and Non-Critical to Function (NCTF) SignalsVCCDQ (BGA Only)Filtered, low noise d

Signal Description84 Datasheet, Volume 16.15 Future Compatibility Signals6.16 Processor Internal Pull-Up / Pull-Down Resistors§ §Table 6-17. Future Co

Datasheet, Volume 1 85Electrical Specifications7 Electrical Specifications7.1 Power and Ground PinsThe processor has VCC, VCCIO, VDDQ, VCCPLL, VCCSA,

Electrical Specifications86 Datasheet, Volume 17.3 Voltage Identification (VID)The VID specifications for the processor VCC and VAXG are defined by th

Datasheet, Volume 1 87Electrical SpecificationshTable 7-1. IMVP7 Voltage Identification Definition (Sheet 1 of 3)VID7VID6VID5VID4VID3VID2VID1VID0HEX V

Electrical Specifications88 Datasheet, Volume 1001010112B0.46000 1 0 1 0 1 0 1 1 A B 1.10000001011002C0.46500 1 0 1 0 1 1 0 0 A C 1.10500001011012D0.4

Datasheet, Volume 1 89Electrical Specifications01010110560.67500 1 1 0 1 0 1 1 0 D 6 1.3150001010111570.68000 1 1 0 1 0 1 1 1 D 7 1.3200001011000580.6

Datasheet, Volume 1 9Revision History§ §Revision NumberDescription Date001 • Initial Release January 2011002• Added Intel® Core™ i7-2677M, i7-2637M, a

Electrical Specifications90 Datasheet, Volume 17.4 System Agent (SA) VCC VIDThe VccSA is configured by the processor output pins VCCSA_VID[1:0].VCCSA_

Datasheet, Volume 1 91Electrical Specifications7.6 Signal GroupsSignals are grouped by buffer type and similar characteristics as listed in Table 7-3.

Electrical Specifications92 Datasheet, Volume 1Control SidebandSingle Ended CMOS Input CFG[17:0]Single EndedAsynchronous CMOS/Open Drain Bi-directiona

Datasheet, Volume 1 93Electrical SpecificationsNotes:1. Refer to Chapter 6 for signal description details.2. SA and SB refer to DDR3 Channel A and DDR

Electrical Specifications94 Datasheet, Volume 1Notes:1. Refers to a component device that is not assembled in a board or socket and is not electricall

Datasheet, Volume 1 95Electrical Specifications7.9.1 Voltage and Current SpecificationsTable 7-5. Processor Core (VCC) Active and Idle Mode DC Voltage

Electrical Specifications96 Datasheet, Volume 1Notes:1. Unless otherwise noted, all specifications in this table are based on post-silicon estimates a

Datasheet, Volume 1 97Electrical SpecificationsNotes:1. The current supplied to the SO-DIMM modules is not included in this specification.Note: Long t

Electrical Specifications98 Datasheet, Volume 1Notes:1. Unless otherwise noted, all specifications in this table are based on post-silicon estimates a

Datasheet, Volume 1 99Electrical SpecificationsNotes:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2.