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Low Power Features

14 Datasheet

Figure 1. Thread Low-Power States

†

Stop

Grant

Core state

break

P_LVL2 or

MWAIT(C2)

C1/

MWAIT

Core state

break

MWAIT(C1)

C1/Auto

Halt

Halt break

HLT instruction

†

/C6

Core State

break

P_LVL4 or

P_LVL6

MWAIT(C4/C6)

STPCLK#

de-asserted

STPCLK#

asserted

STPCLK#

de-asserted

STPCLK#

asserted

STPCLK#

de-asserted

STPCLK#

asserted

halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt

core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)

† — STPCLK# assertion and de-assertion have no effect if a core is in C2 or C4.

— P_LVL6 read is issued once the L2 cache is reduced to zero.

Figure 2. Package Low-Power States

DPRSTP# de-asserted

DPRSTP# asserted

Snoop

serviced

Snoop

occurs

STPCLK# asserted

STPCLK# de-asserted

SLP# asserted

SLP# de-asserted

DPSLP# de-asserted

DPSLP# asserted

Stop

Grant

Snoop

Normal

Stop

Grant

Deep

Sleep

††

Deeper

Sleep

†

Sleep

††

† — Deeper Sleep includes the C4 and C6 states

†† — Sleep and Deep Sleep are not states directly supported by the processor, but rather sub-states of Silverthorne’s C4/C6

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