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Low Power Features

Datasheet 21

Figure 5 shows the relative exit latencies of the package sleep states discussed above.

Note: Figure 5 uses pre-silicon estimates. Silicon based data will be provided in a future

revision of this document.

Figure 5. Exit Latency Table

Latency (µs)

C0 (HFM)

C0 (LFM)

Both threads halted

Most clocks off

C1E

C1 plus frequency and

VID at LFM

Similar to C1 but Intel®

SCH blocks interrupts

C2 plus PLLs off; VID =

cache retention Vcc

Some L2 cache off

C2 plus PLLs off; VID =

C6 powerdown Vcc

L2 cache off

Power (W)

0 0.1 1 10 100

TDP

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 72 73

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Intel AC80566UC005DE Datenblatt Seite 21