Intel FF8062701084601 Datenblatt PDF herunterladen (Seite 56)

Power Management

56 Datasheet, Volume 1

4.3.2.3 Dynamic Power-down Operation

Dynamic power-down of memory is employed during normal operation. Based on idle

conditions, a given memory rank may be powered down. The IMC implements

aggressive CKE control to dynamically put the DRAM devices in a power-down state.

The processor core controller can be configured to put the devices in active power-

down (CKE de-assertion with open pages) or precharge power-down (CKE de-assertion

with all pages closed). Precharge power-down provides greater power savings but has

a bigger performance impact, since all pages will first be closed before putting the

devices in power-down mode.

If dynamic power-down is enabled, all ranks are powered up before doing a refresh

cycle and all ranks are powered down at the end of refresh.

4.3.2.4 DRAM I/O Power Management

Unused signals should be disabled to save power and reduce electromagnetic

interference. This includes all signals associated with an unused memory channel.

Clocks can be controlled on a per SO-DIMM basis. Exceptions are made for per SO-

DIMM control signals such as CS#, CKE, and ODT for unpopulated SO-DIMM slots.

The I/O buffer for an unused signal should be tri-stated (output driver disabled), the

input receiver (differential sense-amp) should be disabled, and any DLL circuitry

related ONLY to unused signals should be disabled. The input path must be gated to

prevent spurious results due to noise on the unused signals (typically handled

automatically when input receiver is disabled).

4.4 PCI Express* Power Management

• Active power management support using L0s, and L1 states.

• All inputs and outputs disabled in L2/L3 Ready state.

Note: PEG interface does not support Hot Plug.

Note: Power impact may be observed when PEG link disable power management state is

used.

4.5 Direct Media Interface (DMI) Power Management

• Active power management support using L0s/L1 state.

Table 4-12. Targeted Memory State Conditions

Mode Memory State with Processor Graphics Memory State with External Graphics

C0, C1, C1E

Dynamic memory rank power down based on

idle conditions.

Dynamic memory rank power down based on

idle conditions.

C3, C6, C7

If the Processor Graphics engine is idle and

there are no pending display requests, then

enter self-refresh. Otherwise, use dynamic

memory rank power down based on idle

conditions.

If there are no memory requests, then enter

self-refresh. Otherwise, use dynamic

memory rank power down based on idle

conditions.

S3 Self-Refresh Mode. Self-Refresh Mode.

S4 Memory power down (contents lost). Memory power down (contents lost)

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