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PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache

ELECTRICAL SPECIFICATIONS

SCLK

2.46V

0.84V

T54

T55

T52

T53

2.97V

0.84V

SMBUSCLK

Figure 4. SMBCLK Clock Waveform

Clock

Signal

V Valid Valid

T7, T29 (Valid Delay)=

T14, T15 (Pulse Wdith)=

2/3 V

for GTL+ signal group; 1.25V for CMOS, and APIC signal groups=

Figure 5. Valid Delay Timings

Clock

Signal

000763z

V Valid

T8, T27 (Setup Time)=

T9, T28 (Hold Time)=

V 2/3 V

for the GTL+ signal group; 1.25V for the CMOS, and APIC signal groups=

Vclk

Vclk 1.25V for BCLK, and PICCLK

Figure 6. Setup and Hold Timings

1 2 ... 23 24 25 26 27 28 29 30 31 32 33 ... 102 103

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Intel 80526KZ667256 Datenblatt Seite 28