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50 Datasheet

2.8.3 MC_SMI_SPARE_DIMM_ERROR_STATUS

SMI sparing DIMM error threshold overflow status register. This bit is set when the per-

DIMM error counter exceeds the specified threshold. The bit is reset by BIOS.

Device: 3

Function: 0

Offset: 50h

Access as a Dword

Bit Type

Reset

Value

Description

13:12 RW0C

0 REDUNDANCY_LOSS_FAILING_DIMM

The ID for the failing DIMM when redundancy is lost.

11:0 RW0C

0 DIMM_ERROR_OVERFLOW_STATUS

This 12-bit field is the per dimm error overflow status bits. The organization is

as follows:

If there are three or more DIMMS on the channel:

Bit 0 = DIMM 0 Channel 0

Bit 1 = DIMM 1 Channel 0

Bit 2 = DIMM 2 Channel 0

Bit 3 = DIMM 3 Channel 0

Bit 4 = DIMM 0 Channel 1

Bit 5 = DIMM 1 Channel 1

Bit 6 = DIMM 2 Channel 1

Bit 7 = DIMM 3 Channel 1

Bit 8 = DIMM 0 Channel 2

Bit 9 = DIMM 1 Channel 2

Bit 10 = DIMM 2 Channel 2

Bit 11 = DIMM 3 Channel 2

If there are one or two DIMMS on the channel:

Bit 0 = DIMM 0, Ranks 0 and 1, Channel 0

Bit 1 = DIMM 0, Ranks 2 and 3, Channel 0

Bit 2 = DIMM 1, Ranks 0 and 1, Channel 0

Bit 3 = DIMM 1, Ranks 2 and 3, Channel 0

Bit 4 = DIMM 0, Ranks 0 and 1, Channel 1

Bit 5 = DIMM 0, Ranks 2 and 3, Channel 1

Bit 6 = DIMM 1, Ranks 0 and 1, Channel 1

Bit 7 = DIMM 1, Ranks 2 and 3, Channel 1

Bit 8 = DIMM 0, Ranks 0 and 1, Channel 2

Bit 9 = DIMM 0, Ranks 2 and 3, Channel 2

Bit 10 = DIMM 1, Ranks 0 and 1, Channel 2

Bit 11 = DIMM 1, Ranks 2 and 3, Channel 2

1 2 ... 45 46 47 48 49 50 51 52 53 54 55 ... 97 98

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