Intel i7-2960XM Datenblatt Seite 61
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Datasheet 61
Register Description
2.10.3 MC_CHANNEL_0_DIMM_INIT_PARAMS
MC_CHANNEL_1_DIMM_INIT_PARAMS
MC_CHANNEL_2_DIMM_INIT_PARAMS
Initialization sequence parameters are stored in this register. Each field is 2^n count.
Device: 4, 5, 6
Function: 0
Offset: 58h
Access as a Dword
Bit Type
Reset
Value
Description
26 RW 0
DIS_3T.
When set, 3T mode will not be enabled as a part of the MRS write to the
RDIMM. The RC2 write to switch to 3T and back to 1T timing before and after an
MRS write will not be done if the bit is set. This bit should be set if the RDIMM
supports auto MRS cycles where the dimm takes care of the 3T switching on
MRS writes.
25 RW 0
DIS_AI.
When set, address inversion will not be disabled as a part of the MRS write to
the RDIMM. The RC0 write to disable and enable address inversion will not be
done. This bit should be set if the RDIMM supports auto MRS cycles where the
dimm takes care of disabling address inversion for MRS writes.
24 RW 0
THREE_DIMMS_PRESENT.
Set when channel contains three DIMMs. THREE_DIMMS_PRESENT=1 and
QUAD_RANK_PRESENT=1 (or SINGLE_QUAD_RANK_PRESENT=1) are mutually
exclusive.
23 RW 0
SINGLE_QUAD_RANK_PRESENT.
Set when channel contains a single quad rank DIMM.
22 RW 0
QUAD_RANK_PRESENT.
Set when channel contains 1 or 2 quad rank DIMMs.
21:17 RW 15
WRDQDQS_DELAY.
Specifies the delay in DCLKs between reads and writes for WRDQDQS training.
16 RW 0
WRLEVEL_DELAY.
Specifies the delay used between write CAS indications for write leveling
training.
0 = 16 DCLKs.
1 = 32 DCLKs.
15 RW 0
REGISTERED_DIMM.
Set when channel contains registered DIMMs.
14:10 RW 0
PHY_FSM_DELAY.
Global timer used for bounding the physical layer training. If the timer expires,
the FSM will go to the next step and the counter will be reloaded with
PHY_FSM_DELAY value. Units are 2^n dclk.
9:5 RW 0
BLOCK_CKE_DELAY.
Delay in ns from when clocks and command are valid to the point CKE is
allowed to be asserted. Units are in 2^n uclk.
4:0 RW 0
RESET_ON_TIME.
Reset will be asserted for the time specified. Units are 2^n Uclk.
- Datasheet, Volume 2 1
- Contents 3
- 4 Datasheet 4
- Datasheet 5 5
- 6 Datasheet 6
- Datasheet 7 7
- 8 Datasheet 8
- Revision History 9
- 10 Datasheet 10
- 1 Introduction 11
- Introduction 12
- 12 Datasheet 12
- 1.2 References 13
- 14 Datasheet 14
- 2 Register Description 15
- 2.3 Device Mapping 17
- Control Registers 24
- Address Registers 25
- Rank Registers 26
- Thermal Control Registers 27
- 2.5 PCI Standard Registers 36
- Identification Register 38
- Express space 39
- 2.6.1 SAD_PAM0123 41
- 2.6.2 SAD_PAM456 43
- 2.6.3 SAD_HEN 44
- 2.6.4 SAD_SMRAM 44
- 2.6.5 SAD_PCIEXBAR 45
- 19:6 RW 46
- 2:1 RW 46
- 2.7 Intel QPI Link Registers 47
- 2.8.2 MC_STATUS 49
- 13:12 RW0C 50
- 11:0 RW0C 50
- 2.8.4 MC_SMI_SPARE_CNTRL 51
- 2.8.5 MC_RESET_CONTROL 51
- 2.8.6 MC_CHANNEL_MAPPER 52
- 2.8.7 MC_MAX_DOD 53
- 2.8.8 MC_RD_CRDT_INIT 54
- 2.8.9 MC_CRDT_WR_THLD 55
- 2.8.10 MC_SCRUBADDR_LO 55
- 2.8.11 MC_SCRUBADDR_HI 56
- 29:28 RW 58
- 25:24 RW 58
- 21:20 RW 58
- 17:16 RW 58
- 13:12 RW 58
- Registers 59
- MC_CHANNEL_1_DIMM_INIT_CMD 60
- MC_CHANNEL_2_DIMM_INIT_CMD 60
- MC_CHANNEL_1_DIMM_INIT_PARAMS 61
- MC_CHANNEL_2_DIMM_INIT_PARAMS 61
- MC_CHANNEL_1_DIMM_INIT_STATUS 62
- MC_CHANNEL_2_DIMM_INIT_STATUS 62
- 2.10.5 MC_CHANNEL_0_DDR3CMD 63
- MC_CHANNEL_1_DDR3CMD 63
- MC_CHANNEL_2_DDR3CMD 63
- 3:2 RW 0 64
- 31:16 RW 0 64
- 15:0 RW 0 64
- 23:20 RW 0 65
- 19:16 RW 0 65
- 7:0 RW 0 65
- MC_CHANNEL_1_RANK_TIMING_A 66
- MC_CHANNEL_2_RANK_TIMING_A 66
- 18:15 RW 0 67
- 14:11 RW 0 67
- 10:7 RW 0 67
- 6:4 RW 0 68
- 3:1 RW 0 68
- MC_CHANNEL_1_RANK_TIMING_B 69
- MC_CHANNEL_2_RANK_TIMING_B 69
- 29:19 RW 0 70
- 18:9 RW 0 70
- 8:0 RW 0 70
- MC_CHANNEL_1_WAQ_PARAMS 75
- MC_CHANNEL_2_WAQ_PARAMS 75
- MC_CHANNEL_1_ADDR_MATCH 81
- MC_CHANNEL_2_ADDR_MATCH 81
- 31:0 RW 0 82
- 2:1 RW 0 82
- Datasheet 83 83
- Register Description 83
- 26:24 RW 0 87
- 23:0 RW 0 87
- 13:4 RW 0 90
- 3:0 RW 0 90
- 2.13 Memory Thermal Control 92
- Throttling (CLTT) 93
- 2.14.2 MC_DIMM_CLK_RATIO 98
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