Intel i7-2960XM Datenblatt Seite 63
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Datasheet 63
Register Description
2.10.5 MC_CHANNEL_0_DDR3CMD
MC_CHANNEL_1_DDR3CMD
MC_CHANNEL_2_DDR3CMD
DDR3 Configuration Command. This register is used to issue commands to the DIMMs
such as MRS commands. The register is used by setting one of the *_VALID bits along
with the appropriate address and destination RANK. The command is then issued
directly to the DIMM. Care must be taken in using this register as there is no
enforcement of timing parameters related to the action taken by a DDR3CMD write.
This register has no effect after MC_CONTROL.INIT_DONE is set.
Device: 4, 5, 6
Function: 0
Offset: 60h
Access as a Dword
Bit Type
Reset
Value
Description
28 RW 0
PRECHARGE_VALID.
Indicates current command is for a precharge command.
27 RW 0
ACTIVATE_VALID.
Indicates current command is for an activate command.
26 RW 0
REG_VALID.
Indicates current command is for a registered DIMM config write Bit is cleared
by hardware on issuance. This bit applies only to processors supporting
registered DIMMs.
25 RW 0
WR_VALID.
Indicates current command is for a write CAS. Bit is cleared by hardware on
issuance.
24 RW 0
RD_VALID.
Indicates current command is for a read CAS. Bit is cleared by hardware on
issuance.
23 RW 0
MRS_VALID.
Indicates current command is an MRS command. Bit is cleared by hardware on
issuance.
22:20 RW 0
RANK.
Destination rank for command.
19:16 RW 0
MRS_BA.
Address bits driven to DDR_BA[2:0] pins for the DRAM command being issued
due to a valid bit being set in this register.
15:0 RW 0
MRS_ADDR.
Address bits driven to DDR_MA pins for the DRAM command being issued due
to a valid bit being set in this register.
- Datasheet, Volume 2 1
- Contents 3
- 4 Datasheet 4
- Datasheet 5 5
- 6 Datasheet 6
- Datasheet 7 7
- 8 Datasheet 8
- Revision History 9
- 10 Datasheet 10
- 1 Introduction 11
- Introduction 12
- 12 Datasheet 12
- 1.2 References 13
- 14 Datasheet 14
- 2 Register Description 15
- 2.3 Device Mapping 17
- Control Registers 24
- Address Registers 25
- Rank Registers 26
- Thermal Control Registers 27
- 2.5 PCI Standard Registers 36
- Identification Register 38
- Express space 39
- 2.6.1 SAD_PAM0123 41
- 2.6.2 SAD_PAM456 43
- 2.6.3 SAD_HEN 44
- 2.6.4 SAD_SMRAM 44
- 2.6.5 SAD_PCIEXBAR 45
- 19:6 RW 46
- 2:1 RW 46
- 2.7 Intel QPI Link Registers 47
- 2.8.2 MC_STATUS 49
- 13:12 RW0C 50
- 11:0 RW0C 50
- 2.8.4 MC_SMI_SPARE_CNTRL 51
- 2.8.5 MC_RESET_CONTROL 51
- 2.8.6 MC_CHANNEL_MAPPER 52
- 2.8.7 MC_MAX_DOD 53
- 2.8.8 MC_RD_CRDT_INIT 54
- 2.8.9 MC_CRDT_WR_THLD 55
- 2.8.10 MC_SCRUBADDR_LO 55
- 2.8.11 MC_SCRUBADDR_HI 56
- 29:28 RW 58
- 25:24 RW 58
- 21:20 RW 58
- 17:16 RW 58
- 13:12 RW 58
- Registers 59
- MC_CHANNEL_1_DIMM_INIT_CMD 60
- MC_CHANNEL_2_DIMM_INIT_CMD 60
- MC_CHANNEL_1_DIMM_INIT_PARAMS 61
- MC_CHANNEL_2_DIMM_INIT_PARAMS 61
- MC_CHANNEL_1_DIMM_INIT_STATUS 62
- MC_CHANNEL_2_DIMM_INIT_STATUS 62
- 2.10.5 MC_CHANNEL_0_DDR3CMD 63
- MC_CHANNEL_1_DDR3CMD 63
- MC_CHANNEL_2_DDR3CMD 63
- 3:2 RW 0 64
- 31:16 RW 0 64
- 15:0 RW 0 64
- 23:20 RW 0 65
- 19:16 RW 0 65
- 7:0 RW 0 65
- MC_CHANNEL_1_RANK_TIMING_A 66
- MC_CHANNEL_2_RANK_TIMING_A 66
- 18:15 RW 0 67
- 14:11 RW 0 67
- 10:7 RW 0 67
- 6:4 RW 0 68
- 3:1 RW 0 68
- MC_CHANNEL_1_RANK_TIMING_B 69
- MC_CHANNEL_2_RANK_TIMING_B 69
- 29:19 RW 0 70
- 18:9 RW 0 70
- 8:0 RW 0 70
- MC_CHANNEL_1_WAQ_PARAMS 75
- MC_CHANNEL_2_WAQ_PARAMS 75
- MC_CHANNEL_1_ADDR_MATCH 81
- MC_CHANNEL_2_ADDR_MATCH 81
- 31:0 RW 0 82
- 2:1 RW 0 82
- Datasheet 83 83
- Register Description 83
- 26:24 RW 0 87
- 23:0 RW 0 87
- 13:4 RW 0 90
- 3:0 RW 0 90
- 2.13 Memory Thermal Control 92
- Throttling (CLTT) 93
- 2.14.2 MC_DIMM_CLK_RATIO 98
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