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Datasheet 39

2.5.7 PCICMD - Command Register

This register defines the PCI 3.0 compatible command register values applicable to PCI

Express space.

Device: 0

Function: 0-1

Offset: 04h

Device: 2

Function: 0-1, 4-5

Offset: 04h

Device: 3

Function: 0-2, 4

Offset: 04h

Device: 4-6

Function: 0-3

Offset: 04h

Bit Type

Reset

Value

Description

15:11 RV 0

Reserved. (by PCI SIG)

10 RO 0

INTxDisable: Interrupt Disable

Controls the ability of the PCI Express port to generate INTx messages.

If this device does not generate interrupts then this bit is not implemented and

is RO.

If this device generates interrupts then this bit is RW and this bit disables the

device/function from asserting INTx#. A value of 0 enables the assertion of its

INTx# signal. A value of 1 disables the assertion of its INTx# signal.

1 = Legacy Interrupt mode is disabled

0 = Legacy Interrupt mode is enabled

9RO0

FB2B: Fast Back-to-Back Enable

This bit controls whether or not the master can do fast back-to-back writes.

Since this device is strictly a target this bit is not implemented. This bit is

hardwired to 0. Writes to this bit position have no effect.

8RO0

SERRE: SERR Message Enable

This bit is a global enable bit for this devices SERR messaging. This host bridge

will not implement SERR messaging. This bit is hardwired to 0. If SERR is used

for error generation, then this bit must be RW and enable/disable SERR

signaling.

7RO0

IDSELWCC: IDSEL Stepping/Wait Cycle Control

Per PCI 2.3 specification this bit is hardwired to 0.

6RO0

PERRE: Parity Error Response Enable

Parity error is not implemented in this host bridge. This bit is hardwired to 0.

5RO0

VGAPSE: VGA palette snoop Enable

This host bridge does not implement this bit. This bit is hardwired to 0.

4RO0

MWIEN: Memory Write and Invalidate Enable

This host bridge will never issue memory write and invalidate commands. This

bit is therefore hardwired to 0.

3RO0

SCE: Special Cycle Enable

This host bridge does not implement this bit. This bit is hardwired to a 0.

2RO1

BME: Bus Master Enable

This host bridge is always enabled as a master. This bit is hardwired to a 1.

1RO1

MSE: Memory Space Enable

This host bridge always allows access to main memory. This bit is not

implemented and is hardwired to 1.

0RO0

IOAE: Access Enable

This bit is not implemented in this host bridge and is hardwired to 0.

1 2 ... 34 35 36 37 38 39 40 41 42 43 44 ... 97 98

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