Intel i7-2960XM Datenblatt

Document Number: 320835-003Intel® Core™ i7-900 Desktop Processor Extreme Edition Series and Intel® Core™ i7-900 Desktop Processor SeriesDatasheet, Vol

10 Datasheet

Datasheet 11Introduction1 IntroductionThe Intel® Core™ i7-900 desktop processor Extreme Edition series and Intel® Core™ i7-900 desktop processor serie

Introduction12 Datasheetsecurity of the system. See the Intel Architecture Software Developer's Manual for more detailed information. Refer to ht

Datasheet 13Introduction• Unit Interval (UI) — Signaling convention that is binary and unidirectional. In this binary signaling, one bit is sent for e

Introduction14 Datasheet

Datasheet 15Register Description2 Register DescriptionThe processor supports PCI configuration space accesses using the mechanism denoted as Configura

Register Description16 Datasheet2.2 Platform Configuration StructureThe processor contains 6 PCI devices within a single physical component. The confi

Datasheet 17Register Descriptionat DID of 2C22h. Device 4, Function 3 contains the thermal control registers for Integrated Memory Controller Channel

Register Description18 Datasheet2.4 Detailed Configuration Space MapsTable 2-2. Device 0, Function 0: Generic Non-core RegistersDID VID 00h 80hPCISTS

Datasheet 19Register DescriptionTable 2-3. Device 0, Function 1: System Address Decoder RegistersDID VID 00h SAD_DRAM_RULE_0 80hPCISTS PCICMD 04h SAD_

2 DatasheetINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO A

Register Description20 DatasheetTable 2-4. Device 2, Function 0: Intel QPI Link 0 RegistersDID VID 00h 80hPCISTS PCICMD 04h84hCCR RID 08h88hHDR 0Ch 8C

Datasheet 21Register DescriptionTable 2-5. Device 2, Function 1: Intel QPI Physical 0 RegistersDID VID 00h 80hPCISTS PCICMD 04h84hCCR RID 08h88hHDR 0C

Register Description22 Datasheet Table 2-6. Device 3, Function 0: Integrated Memory Controller RegistersDID VID 00h 80hPCISTS PCICMD 04h84hCCR RID 08h

Datasheet 23Register Description Table 2-7. Device 3, Function 1: Target Address Decoder RegistersDID VID 00h TAD_DRAM_RULE_0 80hPCISTS PCICMD 04h TAD

Register Description24 DatasheetTable 2-8. Device 4, Function 0: Integrated Memory Controller Channel 0 Control RegistersDID VID 00h MC_CHANNEL_0_RANK

Datasheet 25Register DescriptionTable 2-9. Device 4, Function 1: Integrated Memory Controller Channel 0 Address RegistersDID VID 00h MC_SAG_CH0_0 80hP

Register Description26 DatasheetTable 2-10. Device 4, Function 2: Integrated Memory Controller Channel 0 Rank RegistersDID VID 00h MC_RIR_WAY_CH0_0 80

Datasheet 27Register DescriptionTable 2-11. Device 4, Function 3: Integrated Memory Controller Channel 0 Thermal Control RegistersDID VID 00h MC_COOLI

Register Description28 DatasheetTable 2-12. Device 5, Function 0: Integrated Memory Controller Channel 1 Control RegistersDID VID 00h MC_CHANNEL_1_RAN

Datasheet 29Register DescriptionTable 2-13. Device 5, Function 1: Integrated Memory Controller Channel 1 Address RegistersDID VID 00h MC_SAG_CH1_0 80h

Datasheet 3Contents1Introduction...111.1 Term

Register Description30 DatasheetTable 2-14. Device 5, Function 2: Integrated Memory Controller Channel 1 Rank RegistersDID VID 00h MC_RIR_WAY_CH1_0 80

Datasheet 31Register DescriptionTable 2-15. Device 5, Function 3: Integrated Memory Controller Channel 1 Thermal Control RegistersDID VID 00h MC_COOLI

Register Description32 DatasheetTable 2-16. Device 6, Function 0: Integrated Memory Controller Channel 2 Control RegistersDID VID 00h MC_CHANNEL_2_RAN

Datasheet 33Register DescriptionTable 2-17. Device 6, Function 1: Integrated Memory Controller Channel 2 Address RegistersDID VID 00h MC_SAG_CH2_0 80h

Register Description34 DatasheetTable 2-18. Device 6, Function 2: Integrated Memory Controller Channel 2 Rank RegistersDID VID 00h MC_RIR_WAY_CH2_0 80

Datasheet 35Register DescriptionTable 2-19. Device 6, Function 3: Integrated Memory Controller Channel 2 Thermal Control RegistersDID VID 00h MC_COOLI

Register Description36 Datasheet2.5 PCI Standard RegistersThese registers appear in every function for every device.Note: Reserved bit locations are n

Datasheet 37Register Description2.5.3 RID - Revision Identification RegisterThis register contains the revision number of the processor. The Revision

Register Description38 Datasheet2.5.5 HDR - Header Type RegisterThis register identifies the header layout of the configuration space.2.5.6 SID/SVID -

Datasheet 39Register Description2.5.7 PCICMD - Command RegisterThis register defines the PCI 3.0 compatible command register values applicable to PCI

4 Datasheet2.9.2 TAD_INTERLEAVE_LIST_0, TAD_INTERLEAVE_LIST_1TAD_INTERLEAVE_LIST_2, TAD_INTERLEAVE_LIST_3TAD_INTERLEAVE_LIST_4, TAD_INTERLEAVE_LIST_5T

Register Description40 Datasheet2.5.8 PCISTS - PCI Status RegisterThe PCI Status register is a 16-bit status register that reports the occurrence of v

Datasheet 41Register Description2.6 SAD - System Address Decoder Registers2.6.1 SAD_PAM0123This register is for legacy device 0, function 0 at 90h-93h

Register Description42 Datasheet25:24 RW 0PAM3_LOENABLE. 0D0000h-0D3FFFh Attribute (LOENABLE). This field controls the steering of read and write cycl

Datasheet 43Register Description2.6.2 SAD_PAM456Register for legacy device 0, function 0 94h-97h address space.Device: 0Function: 1Offset: 44hAccess a

Register Description44 Datasheet2.6.3 SAD_HENRegister for legacy Hole Enable.2.6.4 SAD_SMRAMRegister for legacy 9Dh address space. Note both IOH and n

Datasheet 45Register Description2.6.5 SAD_PCIEXBARGlobal register for PCIEXBAR address space.2.6.6 SAD_DRAM_RULE_0, SAD_DRAM_RULE_1, SAD_DRAM_RULE_2,

Register Description46 Datasheet2.6.7 SAD_INTERLEAVE_LIST_0, SAD_INTERLEAVE_LIST_1SAD_INTERLEAVE_LIST_2, SAD_INTERLEAVE_LIST_3SAD_INTERLEAVE_LIST_4, S

Datasheet 47Register Description2.7 Intel QPI Link Registers2.7.1 QPI_QPILCL_L0, QPI_QPILCL_L1This register provides Intel QPI Link Control.2.8 Integr

Register Description48 Datasheet8RW0CHANNEL0_ACTIVE When set, indicate MC channel 0 is active. This bit is controlled (set/reset) by software only. Th

Datasheet 49Register Description2.8.2 MC_STATUSThis register is the MC primary status register.Device: 3Function: 0Offset: 4ChAccess as a DwordBit Typ

Datasheet 52.10.19 MC_CHANNEL_0_ODT_MATRIX_RANK_0_3_RDMC_CHANNEL_1_ODT_MATRIX_RANK_0_3_RDMC_CHANNEL_2_ODT_MATRIX_RANK_0_3_RD...

Register Description50 Datasheet2.8.3 MC_SMI_SPARE_DIMM_ERROR_STATUSSMI sparing DIMM error threshold overflow status register. This bit is set when th

Datasheet 51Register Description2.8.4 MC_SMI_SPARE_CNTRLSystem Management Interrupt and Spare control register.2.8.5 MC_RESET_CONTROLDIMM Reset enabli

Register Description52 Datasheet2.8.6 MC_CHANNEL_MAPPERChannel mapping register. The sequence of operations to update this register is:Read MC_Channel

Datasheet 53Register Description2.8.7 MC_MAX_DODThis register defines the MAX number of DIMMS, RANKS, BANKS, ROWS, COLS among all DIMMS populating the

Register Description54 Datasheet2.8.8 MC_RD_CRDT_INITThese registers contain the initial read credits available for issuing memory reads. TAD read cre

Datasheet 55Register Description2.8.9 MC_CRDT_WR_THLDThis is the Memory Controller Write Credit Thresholds register. A Write threshold is defined as t

Register Description56 Datasheet2.8.11 MC_SCRUBADDR_HIThis register pair contains part of the address of the last patrol scrub request issued. When ru

Datasheet 57Register Description2.9 TAD – Target Address Decoder Registers2.9.1 TAD_DRAM_RULE_0, TAD_DRAM_RULE_1TAD_DRAM_RULE_2, TAD_DRAM_RULE_3TAD_DR

Register Description58 Datasheet2.9.2 TAD_INTERLEAVE_LIST_0, TAD_INTERLEAVE_LIST_1TAD_INTERLEAVE_LIST_2, TAD_INTERLEAVE_LIST_3TAD_INTERLEAVE_LIST_4, T

Datasheet 59Register Description2.10 Integrated Memory Controller Channel Control Registers2.10.1 MC_CHANNEL_0_DIMM_RESET_CMDMC_CHANNEL_1_DIMM_RESET_C

6 Datasheet2.10.39 Error Injection Implementation ...832.11 Integrated Memory Controller C

Register Description60 Datasheet2.10.2 MC_CHANNEL_0_DIMM_INIT_CMDMC_CHANNEL_1_DIMM_INIT_CMDMC_CHANNEL_2_DIMM_INIT_CMDIntegrated Memory Controller DIMM

Datasheet 61Register Description2.10.3 MC_CHANNEL_0_DIMM_INIT_PARAMSMC_CHANNEL_1_DIMM_INIT_PARAMSMC_CHANNEL_2_DIMM_INIT_PARAMSInitialization sequence

Register Description62 Datasheet2.10.4 MC_CHANNEL_0_DIMM_INIT_STATUSMC_CHANNEL_1_DIMM_INIT_STATUSMC_CHANNEL_2_DIMM_INIT_STATUSThe initialization state

Datasheet 63Register Description2.10.5 MC_CHANNEL_0_DDR3CMDMC_CHANNEL_1_DDR3CMDMC_CHANNEL_2_DDR3CMDDDR3 Configuration Command. This register is used t

Register Description64 Datasheet2.10.6 MC_CHANNEL_0_REFRESH_THROTTLE_SUPPORTMC_CHANNEL_1_REFRESH_THROTTLE_SUPPORTMC_CHANNEL_2_REFRESH_THROTTLE_SUPPORT

Datasheet 65Register Description2.10.8 MC_CHANNEL_0_MRS_VALUE_2MC_CHANNEL_1_MRS_VALUE_2MC_CHANNEL_2_MRS_VALUE_2The initial MRS register values for MR2

Register Description66 Datasheet2.10.10 MC_CHANNEL_0_RANK_TIMING_AMC_CHANNEL_1_RANK_TIMING_AMC_CHANNEL_2_RANK_TIMING_AThis register contains parameter

Datasheet 67Register Description18:15 RW 0tddRdTWr. Minimum delay between Read followed by a Write to different DIMMs. 0000 = 2 0001 = 3 0010 = 4 0011

Register Description68 Datasheet6:4 RW 0tddRdTRd. Minimum delay between reads to different DIMMs. 000 = 2 001 = 3 010 = 4 011 = 5 100 = 6 101 = 7 110

Datasheet 69Register Description2.10.11 MC_CHANNEL_0_RANK_TIMING_BMC_CHANNEL_1_RANK_TIMING_BMC_CHANNEL_2_RANK_TIMING_BThis register contains parameter

Datasheet 7MC_RIR_WAY_CH2_6, MC_RIR_WAY_CH2_7MC_RIR_WAY_CH2_8, MC_RIR_WAY_CH2_9MC_RIR_WAY_CH2_10, MC_RIR_WAY_CH2_11MC_RIR_WAY_CH2_12, MC_RIR_WAY_CH2_1

Register Description70 Datasheet2.10.12 MC_CHANNEL_0_BANK_TIMINGMC_CHANNEL_1_BANK_TIMINGMC_CHANNEL_2_BANK_TIMINGThis register contains parameters that

Datasheet 71Register Description2.10.14 MC_CHANNEL_0_CKE_TIMING MC_CHANNEL_1_CKE_TIMINGMC_CHANNEL_2_CKE_TIMINGThis register contains parameters that s

Register Description72 Datasheet2.10.16 MC_CHANNEL_0_RCOMP_PARAMSMC_CHANNEL_1_RCOMP_PARAMSMC_CHANNEL_2_RCOMP_PARAMSThis register contains parameters t

Datasheet 73Register Description2.10.18 MC_CHANNEL_0_ODT_PARAMS2MC_CHANNEL_1_ODT_PARAMS2MC_CHANNEL_2_ODT_PARAMS2This register contains parameters that

Register Description74 Datasheet2.10.20 MC_CHANNEL_0_ODT_MATRIX_RANK_4_7_RDMC_CHANNEL_1_ODT_MATRIX_RANK_4_7_RDMC_CHANNEL_2_ODT_MATRIX_RANK_4_7_RDThis

Datasheet 75Register Description2.10.23 MC_CHANNEL_0_WAQ_PARAMSMC_CHANNEL_1_WAQ_PARAMSMC_CHANNEL_2_WAQ_PARAMSThis register contains parameters that sp

Register Description76 Datasheet2.10.24 MC_CHANNEL_0_SCHEDULER_PARAMSMC_CHANNEL_1_SCHEDULER_PARAMSMC_CHANNEL_2_SCHEDULER_PARAMSThese are the parameter

Datasheet 77Register Description2.10.26 MC_CHANNEL_0_TX_BG_SETTINGSMC_CHANNEL_1_TX_BG_SETTINGSMC_CHANNEL_2_TX_BG_SETTINGSThese are the parameters used

Register Description78 Datasheet2.10.28 MC_CHANNEL_0_EW_BGF_SETTINGSMC_CHANNEL_1_EW_BGF_SETTINGSMC_CHANNEL_2_EW_BGF_SETTINGSThese are the parameters u

Datasheet 79Register Description2.10.31 MC_CHANNEL_0_PAGETABLE_PARAMS1MC_CHANNEL_1_PAGETABLE_PARAMS1MC_CHANNEL_2_PAGETABLE_PARAMS1These are the parame

8 DatasheetTables1-1 References...132-1 Functions

Register Description80 Datasheet2.10.33 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH2Ch

Datasheet 81Register Description2.10.36 MC_CHANNEL_0_ADDR_MATCHMC_CHANNEL_1_ADDR_MATCHMC_CHANNEL_2_ADDR_MATCHThis register specifies the intended addr

Register Description82 Datasheet2.10.37 MC_CHANNEL_0_ECC_ERROR_MASKMC_CHANNEL_1_ECC_ERROR_MASKMC_CHANNEL_2_ECC_ERROR_MASKThis register contains mask b

Datasheet 83Register Description2.10.39 Error Injection ImplementationThe usage model is to program the MC_CHANNEL_X_ADDR_MATCH and MC_CHANNEL_X_ECC_E

Register Description84 Datasheet2.11 Integrated Memory Controller Channel Address Registers2.11.1 MC_DOD_CH0_0, MC_DOD_CH0_1, MC_DOD_CH0_2Channel 0 DI

Datasheet 85Register Description2.11.2 MC_DOD_CH1_0, MC_DOD_CH1_1, MC_DOD_CH1_2Channel 1 DIMM Organization Descriptor Register.Device: 5Function: 1Off

Register Description86 Datasheet2.11.3 MC_DOD_CH2_0, MC_DOD_CH2_1, MC_DOD_CH2_2Channel 2 DIMM Organization Descriptor Register.Device: 6Function: 1Off

Datasheet 87Register Description2.11.4 MC_SAG_CH0_0, MC_SAG_CH0_1, MC_SAG_CH0_2MC_SAG_CH0_3, MC_SAG_CH0_4, MC_SAG_CH0_5MC_SAG_CH0_6, MC_SAG_CH0_7, MC_

Register Description88 Datasheet2.12 Integrated Memory Controller Channel Rank Registers2.12.1 MC_RIR_LIMIT_CH0_0, MC_RIR_LIMIT_CH0_1MC_RIR_LIMIT_CH0_

Datasheet 89Register Description2.12.2 MC_RIR_WAY_CH0_0, MC_RIR_WAY_CH0_1MC_RIR_WAY_CH0_2, MC_RIR_WAY_CH0_3MC_RIR_WAY_CH0_4, MC_RIR_WAY_CH0_5MC_RIR_WA

Datasheet 9Revision HistoryRevision NumberDescription Date-001 • Initial release. November 2008-002 • Updated section 2.2 and Table 2.3. November 2008

Register Description90 Datasheet2.12.3 MC_RIR_WAY_CH1_0, MC_RIR_WAY_CH1_1MC_RIR_WAY_CH1_2, MC_RIR_WAY_CH1_3MC_RIR_WAY_CH1_4, MC_RIR_WAY_CH1_5MC_RIR_WA

Datasheet 91Register Description2.12.4 MC_RIR_WAY_CH2_0, MC_RIR_WAY_CH2_1MC_RIR_WAY_CH2_2, MC_RIR_WAY_CH2_3MC_RIR_WAY_CH2_4, MC_RIR_WAY_CH2_5MC_RIR_WA

Register Description92 Datasheet2.13 Memory Thermal Control2.13.1 MC_THERMAL_CONTROL0MC_THERMAL_CONTROL1MC_THERMAL_CONTROL2Controls for the Integrated

Datasheet 93Register Description2.13.3 MC_THERMAL_DEFEATURE0MC_THERMAL_DEFEATURE1MC_THERMAL_DEFEATURE2Thermal Throttle defeature register for each cha

Register Description94 Datasheet2.13.5 MC_THERMAL_PARAMS_B0MC_THERMAL_PARAMS_B1MC_THERMAL_PARAMS_B2Parameters used by the thermal throttling logic.2.1

Datasheet 95Register Description2.13.7 MC_CLOSED_LOOP0MC_CLOSED_LOOP1MC_CLOSED_LOOP2This register controls the closed loop thermal response of the DRA

Register Description96 Datasheet2.13.9 MC_RANK_VIRTUAL_TEMP0MC_RANK_VIRTUAL_TEMP1MC_RANK_VIRTUAL_TEMP2This register contains the 8 most significant bi

Datasheet 97Register Description2.13.11 MC_DDR_THERM_STATUS0MC_DDR_THERM_STATUS1MC_DDR_THERM_STATUS2This register contains the status portion of the D

Register Description98 Datasheet2.14.2 MC_DIMM_CLK_RATIOThis register is for the Requested DIMM clock ratio (Qclk). This is the data rate going to the