Register Description
80 Datasheet
2.10.33 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0
MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1
MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH2
Channel Bubble Generator ratios for CMD and DATA.
2.10.34 MC_TX_BG_CMD_OFFSET_SETTINGS_CH0
MC_TX_BG_CMD_OFFSET_SETTINGS_CH1
MC_TX_BG_CMD_OFFSET_SETTINGS_CH2
Integrated Memory Controller Channel Bubble Generator Offsets for CMD FIFO. The
Data command FIFOs share the settings for channel 0 across all three channels. The
register in Channel 0 must be programmed for all configurations.
2.10.35 MC_TX_BG_DATA_OFFSET_SETTINGS_CH0
MC_TX_BG_DATA_OFFSET_SETTINGS_CH1
MC_TX_BG_DATA_OFFSET_SETTINGS_CH2
Integrated Memory Controller Channel Bubble Generator Offsets for DATA FIFO.
Device: 4, 5, 6
Function: 0
Offset: E0h
Access as a Dword
Bit Type
Reset
Value
Description
15:8 RW 1 ALIENRATIO. DCLK to BCLK ratio.
7:0 RW 4 NATIVERATIO. UCLK to BCLK ratio.
Device: 4, 5, 6
Function: 0
Offset: E4h
Access as a Dword
Bit Type
Reset
Value
Description
9:8 RW 0 PTROFFSET. FIFO pointer offset.
7:0 RW 0 BGOFFSET. BG offset.
Device: 4, 5, 6
Function: 0
Offset: E8h
Access as a Dword
Bit Type
Reset
Value
Description
16:14 RW 0 RDPTROFFSET. Read FIFO pointer offset.
13:10 RW 0 WRTPTROFFSET. Write FIFO pointer offset.
9:8 RW 0 PTROFFSET. FIFO pointer offset.
7:0 RW 0 BGOFFSET. BG offset.
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