Intel i7-2960XM Datenblatt Seite 87
- Seite / 98
- Inhaltsverzeichnis
- LESEZEICHEN
Bewertet. / 5. Basierend auf Kundenbewertungen
Datasheet 87
Register Description
2.11.4 MC_SAG_CH0_0, MC_SAG_CH0_1, MC_SAG_CH0_2
MC_SAG_CH0_3, MC_SAG_CH0_4, MC_SAG_CH0_5
MC_SAG_CH0_6, MC_SAG_CH0_7, MC_SAG_CH1_0
MC_SAG_CH1_1, MC_SAG_CH1_2, MC_SAG_CH1_3
MC_SAG_CH1_4, MC_SAG_CH1_5, MC_SAG_CH1_6
MC_SAG_CH1_7, MC_SAG_CH2_0, MC_SAG_CH2_1
MC_SAG_CH2_2, MC_SAG_CH2_3, MC_SAG_CH2_4
MC_SAG_CH2_5, MC_SAG_CH2_6, MC_SAG_CH2_7
Channel Segment Address Registers. For each of the 8 interleave ranges, they specify
the offset between the System Address and the Memory Address and the System
Address bits used for level 1 interleave, which should not be translated to Memory
Address bits. Memory Address is calculated from System Address and the contents of
these registers by the following algorithm:
m[39:16] = SystemAddress[39:16] + (sign extend {Offset[23:0]});
m[15:6] = SystemAddress[15:6];
If (Removed[2]) {bit 8 removed};
If (Removed[1]) {bit 7 removed};
If (Removed[0]) {bit 6 removed};
MemoryAddress[36:6] = m[36:6];
The following table summarizes the combinations of removed bits and divide-by-3
operations for the various supported interleave configurations. All other combinations
are not supported.
Note: If any of bits [8:6] are removed, the higher order bits are shifted down.
Removed [8:6] Divide-By-3 Interleave
000 0 None
001 0 2-Way
011 0 4-Way
000 1 3-Way
001 1 6-Way
Device: 4
Function: 1
Offset: 80h, 84h, 88h, 8Ch, 90h, 94h, 98h, 9Ch
Access as a Dword
Bit Type
Reset
Value
Description
27 RW 0
DIVBY3.
This bit indicates the rule is a 3 or 6 way interleave.
26:24 RW 0
REMOVED.
These are the bits to be removed after offset subtraction. These bits correspond
to System Address [8,7,6].
23:0 RW 0
OFFSET.
This value should be subtracted from the current system address to create a
contiguous address space within a channel. BITS 9:0 ARE RESERVED AND
MUST ALWAYS BE SET TO 0.
- Datasheet, Volume 2 1
- Contents 3
- 4 Datasheet 4
- Datasheet 5 5
- 6 Datasheet 6
- Datasheet 7 7
- 8 Datasheet 8
- Revision History 9
- 10 Datasheet 10
- 1 Introduction 11
- Introduction 12
- 12 Datasheet 12
- 1.2 References 13
- 14 Datasheet 14
- 2 Register Description 15
- 2.3 Device Mapping 17
- Control Registers 24
- Address Registers 25
- Rank Registers 26
- Thermal Control Registers 27
- 2.5 PCI Standard Registers 36
- Identification Register 38
- Express space 39
- 2.6.1 SAD_PAM0123 41
- 2.6.2 SAD_PAM456 43
- 2.6.3 SAD_HEN 44
- 2.6.4 SAD_SMRAM 44
- 2.6.5 SAD_PCIEXBAR 45
- 19:6 RW 46
- 2:1 RW 46
- 2.7 Intel QPI Link Registers 47
- 2.8.2 MC_STATUS 49
- 13:12 RW0C 50
- 11:0 RW0C 50
- 2.8.4 MC_SMI_SPARE_CNTRL 51
- 2.8.5 MC_RESET_CONTROL 51
- 2.8.6 MC_CHANNEL_MAPPER 52
- 2.8.7 MC_MAX_DOD 53
- 2.8.8 MC_RD_CRDT_INIT 54
- 2.8.9 MC_CRDT_WR_THLD 55
- 2.8.10 MC_SCRUBADDR_LO 55
- 2.8.11 MC_SCRUBADDR_HI 56
- 29:28 RW 58
- 25:24 RW 58
- 21:20 RW 58
- 17:16 RW 58
- 13:12 RW 58
- Registers 59
- MC_CHANNEL_1_DIMM_INIT_CMD 60
- MC_CHANNEL_2_DIMM_INIT_CMD 60
- MC_CHANNEL_1_DIMM_INIT_PARAMS 61
- MC_CHANNEL_2_DIMM_INIT_PARAMS 61
- MC_CHANNEL_1_DIMM_INIT_STATUS 62
- MC_CHANNEL_2_DIMM_INIT_STATUS 62
- 2.10.5 MC_CHANNEL_0_DDR3CMD 63
- MC_CHANNEL_1_DDR3CMD 63
- MC_CHANNEL_2_DDR3CMD 63
- 3:2 RW 0 64
- 31:16 RW 0 64
- 15:0 RW 0 64
- 23:20 RW 0 65
- 19:16 RW 0 65
- 7:0 RW 0 65
- MC_CHANNEL_1_RANK_TIMING_A 66
- MC_CHANNEL_2_RANK_TIMING_A 66
- 18:15 RW 0 67
- 14:11 RW 0 67
- 10:7 RW 0 67
- 6:4 RW 0 68
- 3:1 RW 0 68
- MC_CHANNEL_1_RANK_TIMING_B 69
- MC_CHANNEL_2_RANK_TIMING_B 69
- 29:19 RW 0 70
- 18:9 RW 0 70
- 8:0 RW 0 70
- MC_CHANNEL_1_WAQ_PARAMS 75
- MC_CHANNEL_2_WAQ_PARAMS 75
- MC_CHANNEL_1_ADDR_MATCH 81
- MC_CHANNEL_2_ADDR_MATCH 81
- 31:0 RW 0 82
- 2:1 RW 0 82
- Datasheet 83 83
- Register Description 83
- 26:24 RW 0 87
- 23:0 RW 0 87
- 13:4 RW 0 90
- 3:0 RW 0 90
- 2.13 Memory Thermal Control 92
- Throttling (CLTT) 93
- 2.14.2 MC_DIMM_CLK_RATIO 98
Verwandte Produkte und Handbücher für Prozessoren Intel i7-2960XM
Prozessoren Intel Pentium D 840 Datenblatt
(106 Seiten)
(106 Seiten)
Prozessoren Intel SL22T Spezifikationen
(35 Seiten)
(35 Seiten)
Prozessoren Intel E3-1275 Datenblatt
(300 Seiten)
(300 Seiten)
Prozessoren Intel Core 2 Quad Q6700 Datenblatt
(98 Seiten)
(98 Seiten)
Prozessoren Intel T1700 Datenblatt
(98 Seiten)
(98 Seiten)
Prozessoren Intel 2 Duo T7500 Datenblatt
(87 Seiten)
(87 Seiten)
Prozessoren Intel L5618 Datenblatt
(64 Seiten)
(64 Seiten)
Prozessoren Intel B940 Datenblatt
(360 Seiten)
(360 Seiten)
Prozessoren Intel core 2 Duo T5850 Spezifikationen
(292 Seiten)
(292 Seiten)
Prozessoren Intel AT80569KJ073N Datenblatt
(102 Seiten)
(102 Seiten)
© 2020, manymanuals.de. Alle Rechte vorbehalten. | 1.023 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Kommentare zu diesen Handbüchern