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Datasheet 49

2.8.2 MC_STATUS

This register is the MC primary status register.

Device: 3

Function: 0

Offset: 4Ch

Access as a Dword

Bit Type

Reset

Value

Description

4RO1

ECC_ENABLED. ECC is enabled.

2RO0

CHANNEL2_DISABLED

Channel 2 is disabled. This can be factory configured or if Init done is written

without the channel_active being set. Clocks in the channel will be disabled

when this bit is set.

1RO0

CHANNEL1_DISABLED

Channel 1 is disabled. This can be factory configured or if Init done is written

without the channel_active being set. Clocks in the channel will be disabled

when this bit is set.

0RO0

CHANNEL0_DISABLED

Channel 0 is disabled. This can be factory configured or if Init done is written

without the channel_active being set. Clocks in the channel will be disabled

when this bit is set.

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Intel i7-2960XM Datenblatt Seite 49