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76 Datasheet

2.10.24 MC_CHANNEL_0_SCHEDULER_PARAMS

MC_CHANNEL_1_SCHEDULER_PARAMS

MC_CHANNEL_2_SCHEDULER_PARAMS

These are the parameters used to control parameters within the scheduler.

2.10.25 MC_CHANNEL_0_MAINTENANCE_OPS

MC_CHANNEL_1_MAINTENANCE_OPS

MC_CHANNEL_2_MAINTENANCE_OPS

This register enables various maintenance operations such as Refreshes, ZQ, RCOMP,

etc..

Device: 4, 5, 6

Function: 0

Offset: B8h

Access as a Dword

Bit Type

Reset

Value

Description

12 RW 1

CS_FOR_CKE_TRANSITION.

Specifies if chip select is to be asserted when CKE transitions with PowerDown

entry/exit and SelfRefresh exit.

11 RW 0

FLOAT_EN.

When set, the address and command lines will float to save power when

commands are not being sent out. This setting may not work with RDIMMs.

10:6 RW 7

PRECASRDTHRESHOLD.

Threshold above which Medium-Low Priority reads can PRE-CAS write requests.

5RW0

DISABLE_ISOC_RBC_RESERVE.

When set this bit will prevent any RBC's from being reserved for ISOC.

3RW0

ENABLE2N. Enable 2n Timing.

2:0 RW 0

PRIORITYCOUNTER.

Upper 3 MSB of 8 bit priority time out counter.

Device: 4, 5, 6

Function: 0

Offset: BCh

Access as a Dword

Bit Type

Reset

Value

Description

12:0 RW 0

MAINT_CNTR.

Value to be loaded in the maintenance counter. This counter sequences the rate

to Refreshes, ZQ, RCOMP.

1 2 ... 71 72 73 74 75 76 77 78 79 80 81 ... 97 98

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