Intel LE80537GF0414M Datenblatt

Doc. # 314079-024 Intel® Core™2 Duo and Intel® Core™2 Solo Processor for Intel® Centrino® Duo Processor Technology Intel® Celeron® Processor 50

Identification Information 10 Specification Update Identification Information Component Identification via Programming Interface The Intel® Cor

Identification Information Specification Update 11 Table 2. CPU Signature for the Intel® Celeron® Processor Stepping CPU Signature A-1 10661h E-

Identification Information 12 Specification Update Figure 2. Intel® Core™2 Duo Mobile Processor (Micro-FCPGA/FCBGA) Production Markings Figur

Identification Information Specification Update 13 Table 3. Intel® Core™2 Duo Processor – Mobile Intel® 945 Express Chipset Family Component Mar

Identification Information 14 Specification Update QDF#/ S-Spec Processor Number Package Processor Stepping FSB (MHz) Speed HFM/LFM (GHz) Notes

Identification Information Specification Update 15 QDF#/ S-Spec Processor Number Package Processor Stepping FSB (MHz) Speed IDA3/HFM/LFM/SLFM4

Identification Information 16 Specification Update QDF#/ S-Spec Processor Number Package Processor Stepping FSB (MHz) Speed IDA3/HFM/LFM/SLFM4

Identification Information Specification Update 17 QDF#/ S-Spec Processor Number Package Processor Stepping FSB (MHz) Speed IDA3/HFM/LFM/SLFM4

Identification Information 18 Specification Update QDF#/ S-Spec Package Processor Number Processor Stepping FSB (MHz) Speed (GHz) Voltage (V) N

Summary Tables of Changes Specification Update 19 Summary Tables of Changes The following table indicates the Specification Changes, Errata, Spe

2 Specification Update INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLI

Summary Tables of Changes 20 Specification Update Note: Each Specification Update item is prefixed with a capital letter to distinguish the p

Summary Tables of Changes Specification Update 21 AM = Intel® Celeron® processor 400 sequence AN = Intel® Pentium® Dual-Core processor AO = Qua

Summary Tables of Changes 22 Specification Update Errata for Intel® Core™2 Duo Processors for Platforms Based on Mobile Intel 945 Express Chips

Summary Tables of Changes Specification Update 23 Number Stepping Stepping Stepping Plans ERRATA B-2 L-2 A-1 AH19 X X X No Fix Code Segment Limi

Summary Tables of Changes 24 Specification Update Number Stepping Stepping Stepping Plans ERRATA B-2 L-2 A-1 AH38 X X X Plan Fix FXSAVE/FXRSTOR

Summary Tables of Changes Specification Update 25 Number Stepping Stepping Stepping Plans ERRATA B-2 L-2 A-1 AH57 X X X No Fix BTS Message May B

Summary Tables of Changes 26 Specification Update Number Stepping Stepping Stepping Plans ERRATA B-2 L-2 A-1 AH78 X X X No Fix Performance Moni

Summary Tables of Changes Specification Update 27 Number Stepping Stepping Stepping Plans ERRATA B-2 L-2 A-1 AH98 X X X No Fix Updating Code Pag

Summary Tables of Changes 28 Specification Update Number Stepping Stepping Stepping Plans ERRATA B-2 L-2 A-1 AH118 X X X No Fix NMIs may not be

Summary Tables of Changes Specification Update 29 Errata for Intel® Core™2 Duo Processors for Platforms Based on Mobile Intel® 965 Express Chips

Specification Update 3 Contents Preface ...

Summary Tables of Changes 30 Specification Update Number Stepping Stepping Stepping Plans ERRATA E-1 M-1 G-2 AH19 X X X No Fix Code Segment Lim

Summary Tables of Changes Specification Update 31 Number Stepping Stepping Stepping Plans ERRATA E-1 M-1 G-2 AH39 Fixed Cache Data Access Req

Summary Tables of Changes 32 Specification Update Number Stepping Stepping Stepping Plans ERRATA E-1 M-1 G-2 AH60 X X X No Fix LBR, BTS, BTM Ma

Summary Tables of Changes Specification Update 33 Number Stepping Stepping Stepping Plans ERRATA E-1 M-1 G-2 AH82 Fixed Debug Register May Co

Summary Tables of Changes 34 Specification Update Number Stepping Stepping Stepping Plans ERRATA E-1 M-1 G-2 AH102 Fixed Performance Monitor

Summary Tables of Changes Specification Update 35 Number Stepping Stepping Stepping Plans ERRATA E-1 M-1 G-2 Errata Affecting Only Intel® Core™2

Summary Tables of Changes 36 Specification Update Errata for Intel® Celeron® Processor 500 Series for Platforms Based on Mobile Intel® 965 Ex

Summary Tables of Changes Specification Update 37 Number Stepping Stepping Stepping Plans Errata A-1 E-1 M-1 AH21 X Fixed Global Pages in the

Summary Tables of Changes 38 Specification Update Number Stepping Stepping Stepping Plans Errata A-1 E-1 M-1 AH41 X Fixed PREFETCHh Instructi

Summary Tables of Changes Specification Update 39 Number Stepping Stepping Stepping Plans Errata A-1 E-1 M-1 AH67 X X X No Fix Performance Monit

4 Specification Update Revision History Document Number Revision Version Description Date 594274 -001 1.0 Initial release of Intel® Core™ 2 D

Summary Tables of Changes 40 Specification Update Number Stepping Stepping Stepping Plans Errata A-1 E-1 M-1 AH94 X Fixed Performance Monitor

Summary Tables of Changes Specification Update 41 Number Stepping Stepping Stepping Plans Errata A-1 E-1 M-1 AH119 X X X No Fix Benign Exception

Errata 42 Specification Update Errata AH1. Writing the Local Vector Table (LVT) When an Interrupt Is Pending May Cause an Unexpected Interrupt

Errata Specification Update 43 AH4. Exception Record (LER) MSRVERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record

Errata 44 Specification Update AH7. General Protection Fault (#GP) for Instructions Greater Than 15 Bytes May Be Preempted Problem: When the

Errata Specification Update 45 AH11. A Write to an APIC Register Sometimes May Appear to Have Not Occurred Problem: With respect to the retire

Errata 46 Specification Update AH14. LER MSRs May Be Incorrectly Updated Problem: The LER (Last Exception Record) MSRs, MSR_LER_FROM_LIP (1DD

Errata Specification Update 47 AH16. Performance Monitoring Event for Number of Reference Cycles When the Processor Is Not Halted (3CH) Does No

Errata 48 Specification Update AH18. Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose

Errata Specification Update 49 AH20. FP Inexact-Result Exception Flag May Not Be Set Problem: When the result of a floating-point operation is

Specification Update 5 Document Number Revision Version Description Date  Updated Summary Table of changes  Revised Errata AH14, AH25, AH26

Errata 50 Specification Update AH21. Global Pages in the Data Translation Look-Aside Buffer (DTLB) May Not Be Flushed by RSM instruction befor

Errata Specification Update 51 AH24. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Ty

Errata 52 Specification Update AH26. Premature Execution of a Load Operation Prior to Exception Handler Invocation Problem: If any of the bel

Errata Specification Update 53 AH28. EIP May Be Incorrect after Shutdown in IA-32e Mode Problem: When the processor is going into shutdown sta

Errata 54 Specification Update AH31. Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate

Errata Specification Update 55 AH33. Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction Execution Results Problem:

Errata 56 Specification Update AH35. Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update Problem:

Errata Specification Update 57 AH38. FXSAVE/FXRSTOR Instructions which Store to the End of the Segment and Cause a Wrap to a Misaligned Base Ad

Errata 58 Specification Update AH41. PREFETCHh Instructions May Not Be Executed When Alignment Check (AC) Is Enabled Problem: PREFETCHT0, PRE

Errata Specification Update 59 AH44. Performance Monitor IDLE_DURING_DIV (18h) Count May Not Be Accurate Problem: Performance monitoring event

6 Specification Update Document Number Revision Version Description Date 355615 -017 1.0  Added AH118  Updated AH8  Updated Summary Tabl

Errata 60 Specification Update AH47. SYSCALL Immediately after Changing EFLAGS.TF May Not Behave According to the New EFLAGS.TF Problem: If a

Errata Specification Update 61 AH50. IA32_FMASK Is Reset during an INIT Problem: IA32_FMASK MSR (0xC0000084) is reset during INIT. Implication

Errata 62 Specification Update AH53. IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly Problem: The IO_SMI bit in SMRAM'

Errata Specification Update 63 AH55. Using Memory Type Aliasing with Memory Types WB/WT May Lead to Unpredictable Behavior Problem: Memory typ

Errata 64 Specification Update AH58. MOV To/From Debug Registers Causes Debug Exception Problem: When in V86 mode, if a MOV instruction is ex

Errata Specification Update 65 AH59. EFLAGS Discrepancy on a Page Fault after a Multiprocessor TLB Shootdown Problem: This erratum may occur w

Errata 66 Specification Update AH60. LBR, BTS, BTM May Report a Wrong Address When an Exception/Interrupt Occurs in 64-bit Mode Problem: An e

Errata Specification Update 67 AH63. Removed Erratum AH64. Returning to Real Mode from SMM with EFLAGS.VM Set May Result in Unpredictable Syst

Errata 68 Specification Update AH67. Performance Monitoring Event FP_ASSIST May Not Be Accurate Problem: Performance monitoring event FP_ASSI

Errata Specification Update 69 AH70. PMI May Be Delayed to Next PEBS Event Problem: After a PEBS (Precise Event-Based Sampling) event, the PEB

Preface Specification Update 7 Preface This document is an update to the specifications contained in the documents listed in the following Affec

Errata 70 Specification Update AH73. An Asynchronous MCE During a Far Transfer May Corrupt ESP Problem: If an asynchronous machine check occu

Errata Specification Update 71 AH75. B0-B3 Bits in DR6 May Not Be Properly Cleared after Code Breakpoint Problem: B0-B3 bits (breakpoint condi

Errata 72 Specification Update AH78. Performance Monitor SSE Retired Instructions May Return Incorrect Values Problem: The SIMD_INST_RETIRED

Errata Specification Update 73 AH81. A MOV Instruction from CR8 Register with 16-Bit Operand Size Will Leave Bits 63:16 of the Destination Regi

Errata 74 Specification Update AH84. Non-Temporal Data Store May Be Observed in Wrong Program Order Problem: When non-temporal data is access

Errata Specification Update 75 AH87. Unaligned Accesses to Paging Structures May Cause the Processor to Hang Problem: When an unaligned acces

Errata 76 Specification Update AH90. Page Access Bit May Be Set Prior to Signaling a Code Segment Limit Fault Problem: If code segment limit

Errata Specification Update 77 AH93. EFLAGS, CR0, CR4 and the EXF4 Signal May Be Incorrect after Shutdown Problem: When the processor is going

Errata 78 Specification Update AH96. Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL Is Counted Incorrectly for PMULUDQ Instruction Proble

Errata Specification Update 79 AH98. Updating Code Page Directory Attributes without TLB Invalidation May Result in Improper Handling of Code

Preface 8 Specification Update Document Title (Doc number) Location Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A: S

Errata 80 Specification Update AH99. Performance Monitoring Event CPU_CLK_UNHALTED.REF May Not Count Clock Cycles According to the Processors

Errata Specification Update 81 AH101. (E)CX May Get Incorrectly Updated When Performing Fast String REP STOS with Large Data Structures Proble

Errata 82 Specification Update AH103. Performance Monitoring Event MISALIGN_MEM_REF May Over Count Problem: Performance monitoring event MISA

Errata Specification Update 83 AH106. A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to an MTRR Mask Problem: The TL

Errata 84 Specification Update AH108. Overlap of an Intel® VT APIC Access Page in a Guest with the DS Save Area May Lead to Unpredictable Beha

Errata Specification Update 85 AH110. BIST Failure after Reset Problem: The processor may show an erroneous BIST (built-in self test) result i

Errata 86 Specification Update AH113 Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang or a Machine Check Exception

Errata Specification Update 87 AH115 VM Exit with Exit Reason “TPR Below Threshold” Can Cause the Blocking by MOV/POP SS and Blocking by STI Bi

Errata 88 Specification Update AH117 RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Ex

Errata Specification Update 89 AH120 IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check Error Reporting Enable Correctly Problem: IA32

Preface Specification Update 9 are removed from the specification update when the appropriate changes are made to the appropriate product specif

Errata 90 Specification Update Status: For the steppings affected, see the Summary Table of Changes.

Errata Specification Update 91 Erratum Affecting Only Intel® Core™2 Duo Mobile Processors on Mobile Intel® 965 Express Chipset Family AH1P. VM

Errata 92 Specification Update AH4P Multi-Core Processors Configured for Single Core Operation May Not Be Able to Enter Intel® Enhanced Deeper

Errata Specification Update 93 AH6P Activation of Intel® Adaptive Thermal Monitor While Intel® Dynamic Front Side Bus Frequency Switching Is Ac

Specification Changes 94 Specification Update Specification Changes AP1: The following specification change is incorporated in the Intel® Core™

Specification Changes Specification Update 95 §

Specification Clarifications 96 Specification Update Specification Clarifications AH1. Removed AH2. Removed AH3. Clarification of TRANSLATI

Documentation Changes Specification Update 97 Documentation Changes Note: Documentation changes for Intel® 64 and IA-32 Architectures Software D