Intel LE80537GF0414M Datenblatt Seite 40
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Summary Tables of Changes
40 Specification Update
Number
Stepping
Stepping
Stepping
Plans
Errata
A-1
E-1
M-1
AH94
X
Fixed
Performance Monitoring Counter MACRO_INSTS.DECODED May
Not Count Some Decoded Instructions
AH95
X
X
X
Plan Fix
The Stack May Be Incorrect as a Result of VIP/VIF Check on
SYSEXIT and SYSRET
AH96
X
X
X
No Fix
Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is
Counted Incorrectly for PMULUDQ Instruction
AH97
X
X
X
No Fix
Storage of PEBS Record Delayed Following Execution of MOV SS or
STI
AH98
X
X
X
No Fix
Updating Code Page Directory Attributes without TLB Invalidation
May Result in Improper Handling of Code #PF
AH99
X
X
X
Plan Fix
Performance Monitoring Event CPU_CLK_UNHALTED.REF May Not
Count Clock Cycles According to the Processors Operating
Frequency
AH100
X
X
X
Plan Fix
Store Ordering May Be Incorrect between WC and WP Memory
Types
AH102
X
Fixed
Performance Monitoring Event BR_INST_RETIRED May Count
CPUID Instructions as Branches
AH103
X
X
X
No Fix
Performance Monitoring Event MISALIGN_MEM_REF May Over
Count
AH104
X
X
X
No Fix
A REP STOS/MOVS to a MONITOR/MWAIT Address Range May
Prevent Triggering of the Monitoring Hardware
AH105
X
Fixed
False Level One Data Cache Parity Machine-Check Exceptions
May Be Signaled
AH106
X
X
X
No Fix
A Memory Access May Get a Wrong Memory Type Following a #GP
due to WRMSR to an MTRR Mask
AH107
X
X
X
No Fix
PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR
Information
AH110
X
X
No Fix
BIST Failure after Reset
AH111
X
X
X
No Fix
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
AH112
X
X
X
No Fix
Instruction Fetch May Cause a Livelock During Snoops of the L1
Data Cache
AH113
X
X
X
No Fix
Use of Memory Aliasing with Inconsistent Memory Type may
Cause a System Hang or a Machine Check Exception
AH114
X
X
X
No Fix
A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to
Memory-Ordering Violations
AH116
X
X
X
No Fix
Using Memory Type Aliasing with Cacheable and WC Memory
Types May Lead to Memory Ordering Violations
AH117
X
X
X
No Fix
RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution Results
AH118
X
X
X
No Fix
NMIs May Not Be Blocked by a VM-Entry Failure
- Including Intel 1
- Specification Update 2
- Contents 3
- Revision History 4
- 6 Specification Update 6
- Preface 7
- Nomenclature 8
- Specification Update 9 9
- Identification Information 10
- Table 3. Intel 13
- 945 Express Chipset Family 13
- Component Markings 13
- 14 Specification Update 14
- Table 2. Intel 14
- 965 Express Chipset Family 14
- 16 Specification Update 16
- Table 1. Intel 17
- Celeron 17
- 18 Specification Update 18
- Summary Tables of Changes 19
- Specification Update 21 21
- Errata for Intel 22
- 24 Specification Update 24
- 26 Specification Update 26
- 28 Specification Update 28
- Based on Mobile Intel 29
- 30 Specification Update 30
- 32 Specification Update 32
- 34 Specification Update 34
- 38 Specification Update 38
- May Terminate Early 38
- 40 Specification Update 40
- Specification Update 43 43
- Specification Update 45 45
- Not Be Accurate 46
- Specification 47
- Address Translations 47
- Specification Update 49 49
- Specification Update 51 51
- Invocation 52
- Specification Update 53 53
- Be Incorrect 54
- Specification Update 55 55
- Specification Update 57 57
- Accurate 59
- Specification Update 61 61
- Specification Update 63 63
- Shootdown 65
- Specification Update 67 67
- Address 68
- IA32_DEBUGCTL[12] Is Set 69
- Software Interrupts 71
- Specification Update 73 73
- Specification Update 75 75
- Specification Update 77 77
- Specification Update 79 79
- Instructions as Branches 81
- Signaled 82
- Information 83
- AH108. Overlap of an Intel 84
- VM Exit 84
- Count Some Transitions 85
- Memory-Ordering Violations 86
- Specification Update 87 87
- Shutdown 88
- Specification Update 89 89
- 90 Specification Update 90
- Erratum Affecting Only Intel 91
- Core™2 Duo Mobile 91
- Processors on Mobile Intel 91
- Be Able to Enter Intel 92
- Enhanced Deeper Sleep 92
- AH6P Activation of Intel 93
- Dynamic 93
- Specification Changes 94
- Specification Update 95 95
- Specification Clarifications 96
- Documentation Changes 97
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