Intel LE80537GF0414M Datenblatt Seite 23
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Summary Tables of Changes
Specification Update 23
Number
Stepping
Stepping
Stepping
Plans
ERRATA
B-2
L-2
A-1
AH19
X
X
X
No Fix
Code Segment Limit Violation May Occur On 4 Gigabyte
Limit Check
AH20
X
X
X
Plan Fix
FP Inexact-Result Exception Flag May Not Be Set
AH21
X
X
X
Plan Fix
Global Pages in the Data Translation Look-Aside Buffer
(DTLB) May Not Be Flushed by RSM instruction before
Restoring the Architectural State from SMRAM
AH22
X
X
X
Plan Fix
Sequential Code Fetch to Non-canonical Address May have
Nondeterministic Results
AH23
X
X
Fixed
VMCALL to Activate Dual-monitor Treatment of SMIs and
SMM Ignores Reserved Bit settings in VM-exit Control Field
AH24
X
X
X
No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and
Crossing Page Boundaries with Inconsistent Memory Types
May Use an Incorrect Data Size or Lead to Memory-
Ordering Violations.
AH25
X
X
X
No Fix
Some Bus Performance Monitoring Events May Not Count
Local Events under Certain Conditions
AH26
X
X
X
No Fix
Premature Execution of a Load Operation Prior to Exception
Handler Invocation
AH27
X
X
X
No Fix
General Protection (#GP) Fault May Not Be Signaled on
Data Segment Limit Violation above 4-G Limit
AH28
X
X
X
No Fix
EIP May Be Incorrect after Shutdown in IA-32e Mode
AH29
X
X
X
No Fix
#GP Fault Is Not Generated on Writing IA32_MISC_ENABLE
[34] When Execute Disable Is Not supported
AH30
X
X
Plan Fix
(E)CX May Get Incorrectly Updated Fast String REP MOVS
or Fast String REP STOS with Large Data Structures
AH31
X
X
X
Plan Fix
Performance Monitoring Events for Retired Loads (CBH)
and Instructions Retired (C0H) May Not Be Accurate
AH32
X
X
X
No Fix
Upper 32 bits of „From‟ Address Reported through BTMs or
BTSs May Be Incorrect
AH33
X
X
X
Plan Fix
Unsynchronized Cross-Modifying Code Operations Can
Cause unexpected Instruction Execution Results
AH34
X
X
X
No Fix
MSRs Actual Frequency Clock Count (IA32_APERF) or
Maximum Frequency Clock Count (IA32_MPERF) May
Contain Incorrect Data after a Machine Check Exception
(MCE)
AH35
X
X
X
No Fix
Incorrect Address Computed for Last Byte of
FXSAVE/FXRSTOR Image Leads to Partial Memory Update
AH36
X
X
X
No Fix
Split Locked Stores May Not Trigger the Monitoring
Hardware
AH37
X
X
Fixed
REP CMPS/SCAS Operations May Terminate Early in 64-bit
Mode When RCX >= 0X100000000
- Including Intel 1
- Specification Update 2
- Contents 3
- Revision History 4
- 6 Specification Update 6
- Preface 7
- Nomenclature 8
- Specification Update 9 9
- Identification Information 10
- Table 3. Intel 13
- 945 Express Chipset Family 13
- Component Markings 13
- 14 Specification Update 14
- Table 2. Intel 14
- 965 Express Chipset Family 14
- 16 Specification Update 16
- Table 1. Intel 17
- Celeron 17
- 18 Specification Update 18
- Summary Tables of Changes 19
- Specification Update 21 21
- Errata for Intel 22
- 24 Specification Update 24
- 26 Specification Update 26
- 28 Specification Update 28
- Based on Mobile Intel 29
- 30 Specification Update 30
- 32 Specification Update 32
- 34 Specification Update 34
- 38 Specification Update 38
- May Terminate Early 38
- 40 Specification Update 40
- Specification Update 43 43
- Specification Update 45 45
- Not Be Accurate 46
- Specification 47
- Address Translations 47
- Specification Update 49 49
- Specification Update 51 51
- Invocation 52
- Specification Update 53 53
- Be Incorrect 54
- Specification Update 55 55
- Specification Update 57 57
- Accurate 59
- Specification Update 61 61
- Specification Update 63 63
- Shootdown 65
- Specification Update 67 67
- Address 68
- IA32_DEBUGCTL[12] Is Set 69
- Software Interrupts 71
- Specification Update 73 73
- Specification Update 75 75
- Specification Update 77 77
- Specification Update 79 79
- Instructions as Branches 81
- Signaled 82
- Information 83
- AH108. Overlap of an Intel 84
- VM Exit 84
- Count Some Transitions 85
- Memory-Ordering Violations 86
- Specification Update 87 87
- Shutdown 88
- Specification Update 89 89
- 90 Specification Update 90
- Erratum Affecting Only Intel 91
- Core™2 Duo Mobile 91
- Processors on Mobile Intel 91
- Be Able to Enter Intel 92
- Enhanced Deeper Sleep 92
- AH6P Activation of Intel 93
- Dynamic 93
- Specification Changes 94
- Specification Update 95 95
- Specification Clarifications 96
- Documentation Changes 97
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