
Summary Tables of Changes
36 Specification Update
Errata for Intel
®
Celeron
®
Processor 500 Series for Platforms Based
on Mobile Intel
®
965 Express Chipset Family
Writing the Local Vector Table (LVT) When an Interrupt Is
Pending May Cause an Unexpected Interrupt
LOCK# Asserted During a Special Cycle Shutdown Transaction May
Unexpectedly Deassert
VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the
Last Exception Record (LER) MSR
DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring
Count for Saturating SIMD Instructions Retired (Event CFH)
SYSRET May Incorrectly Clear RF (Resume Flag) in the RFLAGS
Register
General Protection Fault (#GP) for Instructions Greater than 15
Bytes May Be Preempted
Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
Before Higher Priority Interrupts
The Processor May Report a #TS Instead of a #GP Fault
A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
Programming the Digital Thermal Sensor (DTS) Threshold May
Cause Unexpected Thermal Interrupts
Count Value for Performance-Monitoring Counter
PMH_PAGE_WALK May Be Incorrect
LER MSRs May Be Incorrectly Updated
Performance Monitoring Events for Retired Instructions (C0H)
May Not Be Accurate
Performance Monitoring Event For Number Of Reference Cycles
When The Processor Is Not Halted (3CH) Does Not Count
According To The Specification
Using 2M/4M Pages When A20M# Is Asserted May Result in
Incorrect Address Translations
Writing Shared Unaligned Data that Crosses a Cache Line without
Proper Semaphores or Barriers May Expose a Memory Ordering
Issue
Code Segment Limit Violation May Occur On 4 Gigabyte Limit
Check
FP Inexact-Result Exception Flag May Not Be Set
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